SU1725373A1 - Device for checking pulse sequences - Google Patents

Abstract

The invention relates to automation and digital technology and is intended to test complex synchronization units, controllers, information sensors used in automated control systems, information processing, and communication. The purpose of the invention is to expand the field of application of the device by enabling the devices to be aggregated with an increase in the number of controlled sequences and an increase in the reliability of the control. The goal is achieved by introducing into the device an encoder, a register, a second one-shot, a buffer element, a third, fourth, and five items OR, a group of one-shot, a trigger, and their connections. Reliability is achieved by ensuring the detection and fixation of the number of the input through which the false signal was received. 3 il. (/ WITH

Description

The invention relates to the field of automation and digital technology and is intended to test complex synchronization units, controllers, information sensors used in automated control systems, information processing, and communications.

The purpose of the invention is to expand the field of application of the device by providing the possibility of aggregating devices by increasing the number of controlled sequences and increasing the reliability of control,

The essence of the invention is to provide the possibility of increasing the number of inputs of controlled sequences by connecting the same type of aggregated devices to control pulse sequences without introducing circuit changes inside the device.

and without the use of additional elements, as well as increasing the reliability of control by ensuring the detection and fixation of the number of the input through which the false signal was received.

Introduction to the device of the priority encoder and its connections provides the identification of the number of the input through which the false signal was received.

The introduction of a second one-shot, buffer element and their connections allows to form a pulse recording the number of the input through which a spurious pulse entered the register, as well as a pulse at the signal output of the device.

The introduction of the register and its communications allows fixing the number of the input through which the false signal was received, and outputting it to the information output of the device.

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The third, fourth, and fifth elements of the OR and their connections provide for the aggregation of devices in order to increase the number of inputs of controlled sequences without introducing circuit changes inside the device and without changing external additional elements.

The introduction of a one-shot group allows for reliable recording of the channel number through which a false signal was received, regardless of its duration.

Introducing a trigger for its communications allows you to clearly distinguish the interval control sequence.

FIG. 1 shows a functional diagram of the device: FIG. 2 is a functional diagram of a device for monitoring n x K sequences implemented by combining n proposed devices for controlling K-input sequences; FIG. 3 shows an example of the arrangement of information for monitoring one sequence in the memory blocks of the device modules (at).

A device for controlling pulse sequences (Fig. 1) contains a memory block 1, a first one-shot 2, a first 3 and a second 4 counters, a decoder 5, an encoder 6, a switch 7, a group of elements AND 8, a register 9, a third 10, p 11, fourth 12, first 13 and second 14 elements OR, second one-shot 15, buffer element 16, one-shot group 17.1-17.p, trigger 18, device sync input 19, device code 20 input number.

A single vibrator 2 forms a pulse at its output, the duration of which exceeds the transient time in counter 3 and memory block 1. It is triggered on the falling edge of the pulse generated at the output of the OR 14 element.

Counter 3 is used to record, store, modify, and issue an address for memory block 1. The entry of the start address of the monitored sequence arriving at the D input of the counter 3 from the input 20 of the device is made on the trailing edge of the sync pulse entering the synchronization input of the counter 3 from the input 19 of the device. The address is modified by incrementing the previous address by one at the falling edge of the pulse coming from the output of the element OR 11 to the counting input of counter 3.

Counter 4 is designed to count the number of pulses in the i-th packet of the monitored sequence. The code (N-v) (rfle N is the number of overflows) arriving at the D input of counter 4 from the second output 29 of the block

1 of the memory is recorded on the falling edge of the pulse arriving at its sync input from the output of the one-shot 2. When a pulse arrives from the output of the switch 7 at the counting input of the counter 4, it increases its state by one.

The decoder 5, in accordance with the code received from the first output 34 of the ROM 1, generates control signals to the inputs of the switch 7 and the group of elements And 8, which makes it possible to distinguish the pulses belonging to and not belonging to the monitored sequence.

The priority encoder 6 is designed to form a code for the number of a false signal, which has arrived at the inputs 21 of the device. When two or more signals arrive at its inputs (which is unlikely), it forms the code of the signal number to which the highest priority is set.

The switch 7 serves to generate a pulse to the counting input of the counter 4, if the incoming pulse at the device input 21 corresponds to a controlled sequence of pulse packets.

The group of elements And 8 is designed to isolate spurious pulses arriving at the inputs 21 of monitored sequences. All elements And groups 8, which correspond to the pulses prohibited in this cycle, are opened with zero signals from the output of the decoder 5, therefore any false pulse received at inputs 21 will be passed to the outputs of elements And 8.

Register 9 is intended for recording, storing and issuing on the device output 26 a code of the input number through which a false signal was received. Information is recorded in register 9 on the falling edge of the pulse from the output of the one-shot 15.

The element OR 10 generates a pulse at the first output 25 of the device’s shear pulse, if it is formed inside the device, or has entered its input 23.

The element OR 11 generates a signal to the counting input of the counter 3 and the element OR 14 when moving to the control of the next packet of pulses through one of the inputs 21.

The element OR 12 generates a pulse at the second output 24 of the device’s shear pulse, if it is formed inside the device or entered at its input 22.

The element OR 13 generates a signal when a false signal arrives at one or several inputs 21.

Element OR 14 generates a pulse triggering one-shot 2, if the counter 3 received a new address.

The single-oscillator 15 generates a short pulse, which through the buffer element 16 enters the signal output of the device, and also records the code of the number of the input that sent a false signal to the register 9. The pulse duration generated by the single-oscillator 15 exceeds the transient time in the priority encoder 6 , but less than the duration of the signal at the output of the encoder 6.

The buffer element 16 provides a pass signal to the output 27 of the device.

Group of one-shot 17.1-17. K is designed to generate signals of a predetermined duration, which ensures reliable recording of information in the register 9. Single vibrators 17.1-17 are triggered. To the leading edges of pulses coming from the outputs of elements AND 8.1-S.K, respectively.

The trigger 18 provides a clear selection of the interval control pulse sequence. It switches to a unit at the falling edge of a pulse arriving at its combined I and C inputs. Setting trigger 18 to zero is performed by a single signal at input R.

The device works as follows.

To build a device that provides control of sequences arriving at the m K inputs, a group of devices is combined as shown in Fig. 2. At the same time, the number n of the combined devices, which will be referred to as modules 33.1 -3.33., Is chosen from the condition hk K.

Before the start of operation, the memory elements of all modules are set to their initial state. Circuit initial installation in figure 1 and 2 conventionally not shown.

In the counter 3 modules 33.1 -3.3. Of the input (Fig. 2), the starting address of the monitored sequence is recorded from the clock pulse received at input 32 and then to inputs 19 of all modules.

From counters 3, the starting address goes to the inputs of blocks 1 of the memory of each module, and the codes written in the cells appear at their outputs. If the first pulse packet must arrive at one of the inputs connected to the i-th module, for example, the j-th input of the i-th group of inputs, then the first output of memory block 1 of module 33.i shows the code of the number of this input, which will go to the input of the decoder 5 of this module, and from the second output of block 1 of this module will be read the code N-v, which will go

to the input D of the counter 4. In the remaining modules 33.p (p 1, n, (p) zero codes will be read at the received address from blocks 1 of the memory.

Simultaneously with the recording of the address in the counter 3, the sync pulse from the input 32 will pass through the elements OR 14 modules 33.1-ZZp and will start the one-oscillators 2 with its falling edge. The single-oscillators 2 will generate pulses whose duration exceeds the maximum transient time in the series-connected counter 3 and block 1 memory As a result, after the input of the counter 4 of the module 33.i is wits the code of the number N-V, on the falling edge of the pulse from the output of the one-shot 2, it is recorded in the counter I of the module 33.i. In the remaining modules, the counters will remain at zero. At the same time, the trigger 18 of the modules 33.1-33.p switches to one and opens the switches 7 and the I-8 elements of its modules.

In accordance with the code received at the input of the decoder 5 module 33.i, it will generate a single signal at the ith output and zero at the other outputs. As a result, the i-th output signal of the decoder 5 will open the i-th information input of the switch 7 module 33.i and close the element AND 8.L In the remaining modules, the inputs of the decoder 5 receive zero codes, so the switches 7 of these modules will be closed and elements AND 8.1 - 8.K are open. With the correct implementation of the controlled sequence, the j-th information input of the group of inputs 21 will receive a burst of pulses. The pulses will pass through the switch 7 to the counting input of counter 4, module 33.i, increasing its state by one each time. When the last pulse of a packet arrives at the output of counter 4, an overflow pulse will be formed (which will pass through the element OR 11 to the counting input of counter 3 and increase its state by one, as well as launch one-two p. 33i). At the same time, the overflow pulse through the OR 10 element will pass to the output 25 of module 33.i and as a result of this will go to all modules 33.i 33.1-1, and through the OR 12 element will pass to output 24 and go to the modules 33.1 + 1 - ZZ.p .

Thus, by the overflow impulse formed by the counter 4, module 33.i, all the counters 3 modules 33.1 - ЗЗ.п. will increase their state by one. The readings at the new address, the codes from the outputs of the memory block 1 are fed to the inputs of the decoder 5 and the counters 4 of their modules and, according to the pulses generated by the single vibrator 2, will be recorded into the counters 4, B

As a result, the device proceeds to control the arrival of the next burst of pulses. In the future, the device will function as described above.

Upon completion of the monitored sequence, zero codes will be read from the outputs of memory blocks 1 of all modules 33.1–33. As a result, all outputs of decoder 5 (except zero ones that are not used) will have zero signals and switches 7 of all modules will be closed , and all elements And 8 will be open. Therefore, any impulse received at the output of 21 modules 33.1 -ZZ.p will generate an error signal at the output 30 of the device. At the end of the monitoring interval, a pulse arrives at the device input 31, which passes to the input 28 of all modules and resets the flip-flops 18 to zero. The device will stop functioning until the start of control of the next sequence.

Let us consider in more detail the process of forming the error signal and the code of the channel number through which it arrived.

If the controlled sequence is distorted at any time of the monitoring interval, then the next impulse will go to one of the inputs of 21 modules 33.1-33.p. Since this pulse does not belong to a controlled sequence, it will pass through one of the elements of And 8 (for example, the element of And 8, t module 33.1) and will launch its 17.m single-vibrator and one-shot 15 module 33 as its leading edge. As a result At the output of the encoder 6, according to Wits, the code of the number of the input through which a spurious pulse was received, which is recorded at the falling edge of the pulse from the output of the one-oscillator 15 into the reristor 9 of module 33.1. At the same time, a pulse from the output of the single-vibrator 15 will open the buffer element 16 and pass through it to the output 30 of the device, indicating an error.

The code for the number of the input on which a spurious impulse was received will be issued at the output 26 of module 33.1.

If further one more false pulse arrives at the inputs of the same module, the output number will be written back to register 9, and the output 27 of the module and then the output 30 of the device will receive an error signal.

If several false pulses are simultaneously received at the inputs of one of the modules 33.1 - ZZ.p, the encoder 6 will select the code of the input number to which the highest priority is assigned (among the received false pulses) and its number will be written into register 9 and will be output 26.

Formula of the Invention A device for controlling pulse sequences containing a memory block, first and second counters, a decoder, a switch, a group of elements AND, a first and second elements OR, a first one-shot, the inputs of the controlled sequence of the device being connected to a group of information inputs of the switch and the first by the inputs of the elements of the AND group, the first output of the memory block is connected to the input of the decoder, the outputs of which are connected to the first group of control inputs of the switch and the inverse inputs of the elements And, whose groups of outputs are connected to the input of the first element OR, the switch output is connected to the counting input of the first counter, the second output of the memory unit is connected to the information input of the first counter, the device synchronization input is connected to the first input of the second OR element, and the synchronization input of the second counter, the output of which is connected to the address input of the memory unit, the output of the second element OR is connected via the first one-shot to the synchronous input of the first counter, the input of the code of the device connection sequence number With the information input of the second counter, characterized in that, in order to expand the field of application of the device by allowing the devices to be aggregated with an increase in the number of monitored sequences and increase the reliability of control, an encoder, a register, a second single vibrator, third, fourth and the fifth OR elements, the one-vibrator group, a trigger, the outputs of the AND elements of the group are connected to the inputs of one-vibrator groups, the outputs of which are connected to the inputs of the priority bus the output of which is connected to the information input of the register, the output of the first element OR is connected via the second one-shot with the register synchronization and is the output of the device error, the output of the register is the output of the code of the input number of the false signal of the device , the fourth and fifth OR elements, the first output of the device shift pulse is connected to the second input of the fifth OR element and the second input of the third OR element, the output of which is the first output the device’s pulse pulse, the second device’s pulse input is connected to the third input of the fifth OR element, and the second input of the fourth OR element, the output of which is the second output of the device’s pulse pulse, the output of the fifth OR element, and

I and C inputs of the trigger, the output of which is connected to the second group of control inputs of the switch and the second direct inputs of the AND elements of the group,

the counting input of the second counter, the output 5 of the sign of the end of the control device of the first one-shot is connected to the union connected to the input of the R-flip-flop.

I and C inputs of the trigger, the output of which is connected to the second group of control inputs of the switch and the second direct inputs of the AND elements of the group,

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Claims (1)

Claim A device for monitoring pulse sequences comprising a memory unit, first and second counters, a decoder, a switch, a group of AND elements, a first and second OR element, a first one-shot, and the inputs of a controlled sequence of the device are connected to a group of information inputs of the switch and the first direct inputs of elements AND groups , the first output of the memory block is connected to the input of the decoder, the outputs of which are connected to the first group of control inputs of the switch and the inverse inputs of the elements AND, group of outputs which are connected to the input of the first OR element, the output of the switch is connected to the counting input of the first counter, the second output of the memory unit is connected to the information input of the first counter, the synchronization input of the device is connected to the first input of the second OR and the synchronization input of the second counter, the output of which is connected to the address input of the memory block, the output of the second OR element is connected through the first one-shot to the sync input of the first counter, the input of the device's sequence number code is connected to the information input the second counter, characterized in that, in order to expand the scope of the device by providing the ability to aggregate devices while increasing the number of monitored sequences and increase the reliability of control, it additionally introduces an encoder, a register, a second one-shot, the third, fourth and fifth elements OR, a group of one-shots , a trigger, and the outputs of the elements AND groups are connected to the inputs of one-group vibrators, the outputs of which are connected to the inputs of the priority encoder, the output of which is connected but with the information input of the register, the output of the first OR element is connected through the second one-shot to the register clock input and is the device error output, the register output is the output of the device false input number code, the overflow output of the first counter is connected to the first inputs of the third, fourth and fifth elements OR , the first output of the device shift pulse is connected to the second input of the fifth OR element and the second input of the third OR element, the output of which is the first output of the device shift pulse, W The second input of the device shift pulse is connected to the third input of the fifth OR element and to the second input of the fourth OR element, the output of which is the second output of the device shift pulse, the output of the fifth OR element is connected to the second input of the second OR element and the counting input of the second counter, output 5 of the first a single-vibrator is connected to the combined I- and C-inputs of the trigger, the output of which is connected to the second group of control inputs of the switch and the second direct inputs of the elements AND groups, the input of the sign of the end of the control device soy dinen with R trigger input. Shig. 1 Phage 2 CPuv b