SU1444777A1 - Device for checking sequences of pulses - Google Patents

Abstract

The invention relates to the field of pulsed technology and is intended to verify multichannel pulse sequences. A distinctive feature of the device is that it allows to increase the reliability of control due to the violation of the sequence of the sequence of control pulses of different types of pulses. The aim of the invention is to increase the reliability of the control. The goal is achieved by introducing a one-shot 5, a delay element 1, a register 3, a permanent memory block 1. 2 Il. S (l

Description

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The invention relates to a pulse technique and is intended for testing multichannel pulse sequences in control systems of ground control equipment and communication equipment,

. The purpose of the invention is to increase the reliability of the control.

FIG. 1 shows the functional scheme of the proposed device; in fig. 2 - time diagrams of his work.

The device contains a block of 1 constant memory, a counter 2, a register 3, a multiplexer 4, a single vibrator 5, an element OR 6, a delay element 7, a prohibition element 8, inputs 9 of the controlled-1X sequences, a group of inputs 10 of the control number - sequence, input 11 write resolution and error output 12,

The device works as follows.

Before starting, all the memory elements of the device are reset (the initial state setting circuits are not conventionally shown), and the code of the device inputs 10 is supplied with the code number of the controlled input sequence, which is written to the register 3 by the pulse received To the input 11 of the device, After that, from the corresponding cell of the permanent memory unit 1, the code of the device entry number 91 is read, through which the pulse of the monitored sequence must be received. This code as an address is fed to the input of multiplexer 4, which connects input 91 to the output, after which the device enters standby mode.

If a pulse arrives at the input 91, it will pass to the output of multiplexer 4 and, at its trailing edge, counter 2 will switch to the next state. As a result, the code of the input number 9J will be read from block 1 of the permanent memory. controlled, input sequence, and the multiplexer connects this input to the input of counter 2. Simultaneously, on the leading edge of the pulse at the output of multiplexer 4, a one-shot 5 will work, which will generate a pulse whose duration exceeds the maximum duration spine of impulses

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device inputs 9, plus the delay time of these pulses on elements 6 and 7. As a result, the prohibition element will be closed for the entire duration of the pulse arriving at input 91 and then through the OR 6 elements and the input element 7 for the prohibition element. An error signal on the device's output 12 will not be generated, since the incoming pulse belongs to the controlled sequence (Fig. 2a).

If the next pulse arrives, for example, at the input 9k instead of the input 9j, then it will not pass to the output of multiplexer 4, since the one-shot 5 will not work, with the result that the prohibition element 8 will be opened. As a result, the received false pulse will pass through the element OR 6, the delay element 7 and further through the prohibition element 8, as a result of which an error signal will be generated at the output e 12 of the device (Fig. 26),

At the end of the monitored sequence, the zero code is read from block 1 of the permanent memory, as a result of which none of the inputs 9. will not be connected to the inputs of counter 2 and the one-shot 5, as a result of which any spurious pulse received at the inputs 9 will be detected, i.e. the output of the device 12 will receive an error signal.

Claims (1)

Invention Formula A device for controlling pulse sequences containing a multiplexer, a counter, an OR element and a prohibition element, the inputs of the monitored device sequences being connected to the inputs of the OR element and the information inputs of the multiplexer, the output of which is connected to the counter input of the counter, the prohibition element output is the error output devices, characterized in that, in order to increase the reliability of the control, a one-shot, a delay element, a register and a block of permanent memory, and information input register is a group of inputs specifying controlled rooms. device sequences, the register write enable input is the device write enable number. the register outputs are connected to the first group of address inputs of the permanent memory unit, the second group of address inputs of which are connected to the output group of the counter, the group of outputs of the permanent memory unit is connected to the group of address inputs of the multiplex12 but Fia.g litter, the output of which is connected to the input of the one-shot, the output of which is connected to the prohibition input of the prohibition element, the information input of which is connected to the output of the delay element, the input of which is connected to the output of the OR element.