SU1684786A1 - Discrete sensors input reserved device - Google Patents

Abstract

The invention relates to automation and computing technology and can be used in automated monitoring and control systems for entering information into a control computer about the state of discrete sensors or in devices for recording statistical data on the state change of two-position sensors, and could also used in devices using circuit methods to improve the reliability of operation. The aim of the invention is to increase reliability due to pro simplified R & D. The device contains a group of blocks 1 into the block, each of which contains from the first to the third element s matching 2-4, from the first to the third majority elements 5-7. first delay element 8, single-vibrator 9.register 10, galvanic isolation unit 11, switch 12, second 13 and third 14 delay elements, trigger 15, first AND 15 element, counter 17, second AND 18 element, multiplexer 1P, first to third amplifiers 20 22 1 c p f-crystals. 1 il. 1Л С

Description

The invention relates to automation and computer technology and can be used in automated monitoring and control systems for entering information into a control computer about the state of discrete sensors or in devices for recording statistical data on the state of two-position sensors, as well as devices using circuit methods to increase the reliability of operation.

The aim of the invention is to increase the hardware reliability and operation of the device by simplifying it.

The drawing shows the functional diagram of the device.

The device contains a group of input units 1, each of which contains the first to the third matching elements 2-4, the first to the third major elements 5-7, the first delay element 8, the single vibrator 9, the register 10, the galvanic switch unit 11, the switch 12, the second i3 and the third 14 slug the delay of three; rep 15, first IS-NOT 16, counter 17, second IS-NOT 18, multiplexer 19, first to third amplifiers 20-22, first to third 23.1-23.3 inputs Sync the device, first to third 24.1-24.3 inputs Device data from the first to the third 25.1-25.3 inputs Sampling device, from the first to the third 26.1-25.3, 27 1-27 3. 28.1-28.3 outputs, respectively, cm cm Synchronization, Data, Selectable

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triple, from first to third 29.1-29.3 output data bus from the first to the third input block 1, the information inputs of the device 30,31.1,32.1,33.1 - the majority outputs of the synchronization signals, Data and Sampling of the first input block 1,

31.2,32,2.33.2-second input block 1.31.3.

32.3,33.3 - the third input block 1. The device operates as follows.

In each unit 1 of the device, the signals Synchronization, Data, Sample, which form the interrogation address of a group of discrete sensors at the output of register 10 via elements 2–4 of matching input signals, are fed through a communication interface module with peripheral devices from a computer via inputs 23.1–23.3, 24.1- 24.3, 25.1- 25.3, respectively. The synchronization signal from the outputs 31.1-31.3 of the element 2 matching the input signals of each block enters the majority element 5 and then through the first delay element 8 arrives at the clock input of the register 10, the data signal from the outputs 32.1-32.3 of the element 3 matching each block enters the majority element 6 and to the information input of register 10, the signal Sampling from the outputs 33.1-33.3 of element 4 of matching each block is fed to the majority element 7 and to the enabling input of register 10. Upon termination of the signal Sample from the output of element 7 A one-shot 9 is activated, removing the signal to prohibit the output of the sensor polling address to switch 12. An array of discrete sensor states through inputs of 30 circuits of discrete sensor states through an element 11 of galvanic isolation of sensor input circuits is fed to inputs of switch 12. Data of a group of discrete sensors by A given polling address from the switch 12 is fed to the first inputs of the multiplexer 19 of its channel and the second inputs of the multiplexer of the backup channel. At the same time, information is recorded in multiplexer 19 by a clock input from the output of the second element IS-NOT 18, to the first input of which a recording resolution signal is received from the inverse output of the trigger 15, and to the second input is a signal from the output of the second element 13 after it ends signal action Sampling from the output of the majority element 7. Delay of the termination signal Sampling on the second delay element 13 ensures the normal passage of discrete sensor data to the input of the multiplexer 19. Simultaneously from the output of the start element 13 third element 14 delay, output

which arrives at the information input of the trigger 15. When a trigger of the trigger of the pulse front 15 arrives at the clock input of the synchronization from the output of the majority

element 5, the trigger 15 goes to state 1, allowing the passage of counting pulses through the first element AND-NOT 16 to the counting input of counter 17. The output of counter 17 generates a search for the addresses of the multiplexer 19. The overflow signal from the output of counter 17 resets the trigger 15. Information The state of discrete sensors enters the computer at a given address from amplifiers 20-22 output signals. With

5 of this, the signals are received from the output of the multiplexer 19 and then through the nipple 20 to the input of the interface module of the computer communication, the Sample signals are received from the direct output of the trigger 15 through the amplifier 21,

0 signals Synchronization - from the output of the element 5 through the amplifier 22. Thus, the input of data about the state of discrete sensors into the computer is carried out at a given polling address by sequentially transmitting a group of data to the computer interface module.

Claims (2)

Claim 1. Reserved device for inputting information from discrete sensors, containing a group of input blocks, characterized in that, in order to increase the reliability of the device, the information inputs of the group input blocks are combined and are the information inputs of the device, the Sync, Data and Sample inputs which are the corresponding inputs of the input blocks, the outputs Synchronization, Data and Sampling which are respectively the outputs of Sync, Data and Sampling of the device, output buses of data about The bottom blocks of the group input are connected to the input data buses of other blocks of the group input, and the majority outputs 5 Sync, Data and Sampling signals of one group input blocks are connected to the corresponding majority inputs of other group input blocks. 0 2. The device pop. 1, differs in order. that the input block contains three matching elements, three major elements, three delay elements, a one-shot, a register, a trigger, two NAND elements, a multiplexer, a counter, a switch, three bodies and an electrical isolation unit, whose inputs are connected to the information inputs and the outputs - with the information inputs of the switch, the address inputs of which are connected to the outputs the register, the clock input of which is connected to the output of the first delay element, whose input is connected to the input of the first amplifier, the first input of the first NANDE, the clock input of the trigger and the output of the first major element, the first and second inputs of which are the block synchronization inputs, and the third input is connected to the synchronization output of the block synchronization and the output of the first matching element, the input of which is the synchronization input of the block, the register information input is connected to the output of the second major an element, the first and second inputs of which are the majority inputs of the block data, and the third input is connected to the majority output of the block data and the output of the second matching element whose input is the input of the block data, the register enable input is connected to the inputs of the one-shot and the second delay element and the output of the third major element, the first and second inputs of which are the majority inputs of the block sampling, and the third input is connected to the major output of the block sampling and the output of the third element of the blocking, the output of the single-vibrator is connected to the sample input of the crystal register, the output of the second delay element is connected to the second input of the second NAND element and the input of the third delay element, the output of which is connected to the trigger information input, the reset input which is connected to the overflow output of the counter, the outputs of which are connected to the address inputs of the multiplexer, the gate input of which is connected to the output of the second NAND element, the first input of which is connected to the input reset and the counter and the reverse trigger output, the direct output of which is connected to the input of the third amplifier and the second input of the first NAND element, whose output is connected to the clock input of the counter, the switch outputs are the output data buses of the block and are connected to the second group of information inputs of the multiplexer, the first group of information inputs of which are connected to the input data bus of the block, and the output is connected to the input of the second amplifier whose output is the output of the data of the block, the outputs of the first and third amplifiers are respectively, the outputs Sync and Sample block. thirty