SU1246084A1 - Device for registering state of monitored object - Google Patents

Abstract

The invention relates to the field of supervisory technology and can be used in automation devices and process control systems to control the correctness of information exchange between components and blocks. The purpose of the invention is to expand the functionality by registering asynchronous signals. The device contains signal drivers, the second outputs of which are connected to the corresponding information inputs of registers, the first outputs - to the inputs of the OR element, and inputs of the signal conditioners are connected to the corresponding inputs of the device, and the summing input of the counter is additionally connected to the synchronization inputs of the registers. In addition, the device contains two AND elements, an OR element and an OR-NOT element whose output is connected to one of the inputs of the first AND element, the output of which and the output of the second element AND through the OR element are connected by the counter input. The device provides registration of a specified number of signals on p inputs taking into account their arrangement in time, 2 sludge (L N9 0 Od O 00 4

Description

The invention relates to computing technology, is intended to control the correctness of transmitted signals in parallel circuits of communication between central and peripheral devices of various kinds of computer complexes and can be used in automation devices and process control systems to control the correctness of information exchange between components, and blocks,

The purpose of the invention is to expand the functionality by registering asynchronous signals about

Fig in the functional diagram of the device; FIG. 2 is a time diagram.

The device contains a group of shapers 1.1 1OP signals, the second element OR 2, the second element OF, the counter 4, the decoder 5, the group of registers 6 - the shift bias, the first element AND 7, the first element OR 8, the element OR NOT 9, the inputs 10 Start and 11 Reset with

The device works in a clean way.

When the signal is triggered, the trigger on input 10 triggers element 3 and 1 element OR records into counter 4 a unit that appears on the second output of the decoder 5, respectively, zero is set at its first output, which causes element 3 to close, but through Element ШШ-НЕ 9 element 7 is denied. After that, the inputs XI, X2, ..., Xn can receive information (signal) in any temporal arrangement. Assume that signals XI, X2, ... Xn appear in the sequence shown in the timing diagram (Fig. 2), when already when a signal appears at input 10, the first signal at the output of the element OR 8 will record a unit of information in the first bit register b. The formers 1 "1 - 1.p are built in such a way that their input resistance is large, therefore, when the inputs XI, X2, o, Xp are connected to the controlled circuit, the information between the transmitting and receiving devices. The shape and duration of the signals at the second output of the formers 1.1 - 1, n repeats the shape and duration of the signals at the inputs XI, X2, „. ,, Xn. At the first exit of each

ten

460842

the driver generates signals from the edges of the incoming input signals, which in turn are fed to the element OR 2 and further to the output 5 of the element OR 8.

Thus, when a signal arrives at input X2 in register 6.1, the unit shifts to the second bit and the unit is written to the first bit and at the same time the unit is written to the first bit of the 6.2 register. When the signal at input XI disappears, two units shift to the second and third bits and write zero 15 to the first digit of the register 6.1, the shift

units in the second register bit 6.2. and re-writing the unit for the first bit of this register.

Each time a signal arrives or disappears at any of the inputs XI, X2, ..., Xn, information is shifted by one bit in each register and the unit is written to the first bit of that register, to the input of which POST71IL signal from the corresponding input XI, X2 , ..., Xn, and counter 4 calculates the number of shifts to the value of m.

When the t-signals from the element OR 8 arrive at the m-output of the decoder 5, a unit appears which closes the input of the element 7 through the element OR-NOT 9, the counter stops, the signals to the input 6 of the registers do not pass. maximum number of signal edges20

25

35

catches that can be received for all chains in one exchange cycle (or double the sum of signals for all inputs XI, X2 Xp per exchange cycle).

If the number of signals at the inputs XI, X2, ..., Xn per exchange cycle is greater than t, then in the registers the entry is recorded with information only from the t-signals (fragment) of the exchange signals. And if the temporal alignment of the exchange signals in one cycle (for example, for a test task) is known in advance, then it is easy to find the known alignment of signals with the state of register bits, to detect whether the signals are exchanged correctly or incorrectly, and in which circuit is incorrect.

5s

Claims (1)

Invention Formula A device for registering the condition of the NIN of the object under control, containing an archetype. a group of shift registers, a group of signal conditioners, an OR trigger element, a counter, AND elements, the inputs of the group signal conditioners are connected to the outputs of the object being monitored, and the outputs of the group shift registers are device outputs, the output of the first AND element is connected to the first input of the first OR element, characterized in that, in order to extend the functionality by registering asynchronous signals, the OIO contains a second OR element, an OR-NOT element and a decoder, the counter outputs being connected to the input Ams of the decoder, the first output of which is connected to the first inputs of the second element AND and the element OR NOT, VyA60844 the stroke of which is connected to the first input of the first element I, the second input of which is connected to the output of the second element OR, whose inputs are connected to the first outputs of the group of signal conditioners, the second outputs connected to the information inputs of the group shift registers, whose sync inputs and counting input the counter 10 is connected to the output of the first OR element, and the reset inputs - and the counter reset input - to the device reset input, the second output of the decoder is connected to the second input 15 of the element OR NOT, the second input of the second element AND is connected to the start input of the device, and the output is connected to the second input of the first element OR. F {4b.1 FIG. 2