SU1193655A1 - Serial code-to-parallel code converter - Google Patents

Abstract

1. A SERIAL CODE TO PARALLEL TRANSMITTER, containing a clock, a shift register, an output register, a control unit, a command register, the information input of the shift register is connected to the first information input of the converter, the command register input is the input of the converter mode, and the first output connected to the first input of the control unit, allowing the output of which is connected to the control input of the output register, the output of which is the information output of the conversion bodies, characterized in that, in order to increase the reliability of work, a comparison circuit, first and second subtractive counters, an odd parity control node, two OR elements, a trigger, an IC1 OR signal conditioner, and a first and second information inputs are introduced into it. the converter through the EXCLUSIVE OR element is connected to the first input of the first OR element, the second input of which is connected to the output of the command register, and the output to the shift inputs of the shift register and the counting input of the first deducting account The reset input of which and the reset inputs of the trigger of the second subtractive counter and the control node for oddness are connected to the output of the second OR element, the first input of which is connected to the output. The end of the block word is simplified, and the second input is the start input of the converter, the first information input of which is connected to the information input of the control node to oddness, the output of which is connected to the second input of the control unit, the third input of which is connected to the output of the comparison circuit, the first and second inputs of which are connected We correspond to (Least with the output of the first and first with the output of the second subtractive counters, the output of the command register is connected to the control input of the shift register, the output of which is connected to the information input of the output register, the output of the clock generator from the pulses is connected to the clock input of the request signaling generator, One trigger input and a gate input of which are connected to the trigger output and the first output of the second subtractive counter, respectively, the second output of which is connected to the second input of the trigger and quad rtym input control unit, the output of the request signal is connected to the counting input of the counter and the second subtracter is output request transducer, third and fourth outputs of the control unit are respectively outputs true and Invalid converter, wherein the control unit comprises a switch.

Description

counter, eight elements AND, two elements NOT, trigger and three delay elements, the information inputs of the switch and the counter form the first input, the block, the information outputs of the counter are connected to the control inputs of the switch, the control input of the counter is connected to the output of the first element: And , the first input of which and the first input of the second element I are connected to the first output of the trigger :, the switch output is connected to the second input of the second element I, the output of which is connected to the first input of the third element AND whose output is With the permitted output of the block, the output of the counter is connected to the first input of the fourth element I, the output of which is connected to the second input of the first element I and is the OUTPUT. The end of the block word, the first inputs of this and the sixth element I are connected respectively to the left and second output trigger, the first and second inputs of which are connected respectively to the outputs of the seventh and eighth elements AND, the second input of the fourth element 11 through the first delay element is connected to the output of the second element 93655

The delay element connected to the second inputs of the third, fifth, and sixth terminals, the outputs of the fifth and sixth elements, and are respectively the outputs of the True and Incorrect unit, the fourth input of the block is connected to the input of the second delay element and through the third delay element - with the first inputs of the seventh and eighth elements are And, the second and third entrances of the eighth element And are connected to the second and third inputs of the block, through the first and second elements are NOT connected to the second and third inputs of the seventh element I.

2. The converter according to claim 1, of which is that the request signal conditioner contains a desfrrator, a trigger and an And element, with -.

What clock, trigger and gating inputs of the imaging unit are connected With a group of inputs of the decoder, the first and second outputs — which are connected to the R- and S inputs of the trigger;

ra, the output of which is connected to the lane. the input of the element And, the second input and the output of which are connected respectively to the clock input n the output of the imager.

. . ,

..-.

The invention relates to a computational technique and automatic transmission and conversion of data and can be used in computer input systems from a source of information form 1 located at a distance of up to 200 m.

The aim of the invention is to increase the reliability of work.

Figure 1 shows a schematic conversion; Fig 2 is a block diagram of the control unit; figure 3 - diagram of the request signal generator.

The converter contains 1 clock pulse generator, shaper 2 request signals, first subtracted counter 3, shift register 4 gH, trigger 5, information output bJ comparison circuit 7, second subtraction counter 8, control block 9, elements 10 and 11, output register 12, node 13 control for oddness, .element EXCLUSIVE 1-SHI 1A, command register 15, information inputs 16 and 17, command input 18, input

19 start, exit 2U request, outputs Wrong 21 and True 22..

The control unit contains the switch 23, the counter 2A, the And 2532 elements, the trigger 33, the delay elements 34-36, the FIE elements 37 and 38.

The request signal shaper contains a decoder 39, trigger 40, element 41.

1 clock pulse generator

designed for high-impulse corner pulses. The start of the former 2 is carried out by sending a permitting signal to its second input. la trigger 5 and if available on

the third inputs of the binary code 10001 (number 33,) from counter 3.

31

At the same time, a pulse appears at the first output of the decoder 39, which sets the trigger 40 to 1. The clock pulses are allowed to pass through the AND 41 element to the output of the driver 2 request signals.

 When code 00000 appears, an impulse appears at the input of the deashfrater, at its second output, which sets the trigger 40 to O. The output of the request signals is stopped. The first, second, third outputs of the former 2 are the first, second, third inputs of the disinfector 39.

The output of the AND 41 element is the output of the driver 2 and is connected to the input of the counter 3.

Counter 3 controls the operation of the imaging unit 2, counts the number of request signals issued, and, when zeroed, produces a gate pulse.

Before each cycle in the counter 3, the number 10001 is recorded at the first input set. The counter operates on the subtraction.

Shift register 4 is intended to be filled with input information. The outputs of the register 4 are connected to the second inputs of the output register. The trigger 5 is designed to issue a permitting signal to the driver 2 of the request signal when an element OR signal is received at its first input. 11.

Circuit 7 compares the codes from counters 3 and 8, with equality at its output 1.

The counter 8 is designed to count the number of information bits arriving at the first inputs 17 and 16 of the device, i.e. signals Log.1 and Log.O, respectively.

The counter 8 operates on the subtraction, the number 10001 is preliminarily recorded at the installation input. The counting outputs of the counter 8 are connected to the second inputs of the comparison circuit 7.

The control unit 9 receives the command code from the command register 15 and writes it to the counter 24. In the code written to the counter, the number of information words to be received from the information source is indicated, the code entering the switch 23 outputs indicates the order of rewriting information from register 12 shift. Change Your Own 936554

Stand, the counter 24 connects one of the inputs of the switch 23 to its you: turn. When resetting, the counter 24 transmits a signal O, 5 to its second output, indicating the end of the reception of information. After receiving the 33 pulses, the comparison circuit 7 and the node 13 of the control for odd parity produce signals 1 and on the third and second inputs of the control block 9

10 laziness, and counter 3 gates the 1st pulse to the fourth input. The delay element 36 increases the duration of the input pulse. At the input of the AND element 32, a signal appears

15 establishing the trigger 33 in 1 .. In the absence of signals from the comparison circuit 7 and (or) the odd parity control node 13, a signal appears at the output of the AND element 31, which sets the trigger 33 to O. This state indicates incorrect reception of information. The outputs of the elements And 27-30 are the outputs of the control block 9.

25 Output register J2 is designed to receive information words from the shift register and store them during the reception cycle of one information-. | tion word.

Node 13 Odd Control

30 checks for the receipt of the information code for oddness. With the correct transmission and reception in the information code there will always be an odd number 1, therefore, in this device, as a circuit that implements the odd parity check function, a trigger can be used with a counting input and installation in O.

The EXCLUSIVE OR 14 element is designed to generate w clock pulses required to advance information in shift register 4. It eliminates the appearance of a signal at the output while the signals appear simultaneously, i.e. interference at its two inputs.

The command register 15 serves to receive a command from a computer, store it and issue it to the control unit 9, and in

0 offline mode test program, converter checks, i.e. serves as a simulator of the source of information.

The device works as follows.

The register of 15 commands from a computer memory on input 18 is entered into an input command, in which the order of the transfer is indicated.

 information from the register 4 shift, the number of information words and bits in the word and other signs. Depending on the type of received information, the corresponding codes are transmitted to the first input of block 9 of register 15. Filling of the shift register 4 occurs completely in each cycle. The filling of the output register 12 may not occur in every wild.

With a small delay relative to the input command to the input 19 of the converter, a signal is received that passes through the element. 1-ШИ 11, 15 writes the number 33 into counters 3 and 8, sets the control unit 13 to O, trigger 5 to 1. Upon receiving the enabling signal, the driver of the 2 request signals issues signals to the source-20 nickname information. Counter 3, counting 33 pulses, is zeroed. Upon the appearance of a zero code at the input of the imager 2, the output of the request signals is stopped, the trigger 5 is set to 0 by a pulse from the output of the counter 3. In response, k;

the source of the request generates a request to the inputs 16 and 17 of the pulse converter of the information code Log. 30 1 or Log. About, respectively, the first pulse-control bit.

Log.1 1-SHI Log.o of the information code is fed to the input of the 35 EXCLUSIVE SHSh 14, which generates clock shift pulses. These pulses through the element OR 10 are fed to the input of the shift register 4 and the counter 8. From the input 17, the signal 0 Log.1 arrives at the information input of the pepiCTpa 4 shift and the control unit 13 for oddness, register 4 is filled, and the oddness of the received that code. 5 The absence of a signal at the first input of register 4 and the presence of a shifting clock pulse is perceived as a Log.o. Counter 8, counting 33 pulses, is zeroed. Circuit 7 of comparison compares the codes of counters 3 and 8 and, if its output 1 is equal, which enters the input of block 9, counter 8 is zeroed a little later.

Counter 3 due to the delay of 55 distribution of signals in the communication line between the converter and the source

information.

This delay is compensated for by increasing the pulse duration from the first output of the counter 3 to the control block 9. This function is performed by delay element 36.

With a certain delay of the time determined by the delay element 35, depending on the code arriving at the first inputs of the AND elements 27 - 30, signals appear on their inputs. The ProCurder records information in you. the input register 12, the signal is true, and also in the element OR 11, indicating the end of the cycle and the beginning of a new one. The source of the information, having received the signal True prepares a new information word for transmission. Cyclic is repeated. Thus, the entire array of information is received.

If interference appears in the communication line, goes to inputs 17 or 16, and can be perceived by the converter as useful signals, while the counter 8 counts a large number of pulses, the comparison circuit 7 pushes O into the control unit, the trigger 33 is set to O. The odd parity check circuit can signal o, if the code is even, trigger 33 is also set to O. A similar happens, ecnvi will receive fewer pulses in counter 8. The control block 9 generates a signal incorrectly and a signal about the end of the cycle. Record information at. this does not happen and since the prohibitating signal O is deducted from the second input of the element AND 25, then subtraction 1 from the counter 24 will not occur. Upon receipt of a signal, the source of information is incorrectly repeated the transmission of the incorrectly received information word. The information in output register 12 may be stored for the duration of the filling of the shift register 4. The capacity of registers 4 and 12 is 4 bytes, chosen from the conditions of the speed of the computer and the time of reception of the entire array of information. From these same conditions, the frequency of oscillator 1 is selected.

In offline mode, the information from the second input of the register 13 commands is fed to the input of the register 4 shift. Filling in the test information of registers 4 and 12 is the same as from the source: .icon information. By software comparison of the test and information obtained at the output of register 12, it is possible to judge the health of the converter.

The use in this device of a save of information reception according to the type of request - answer allows not synchronizing the frequency of the clock feHerator and the frequency of arrival of the input information bits. The ISKGPO1AUSCHE OR element suppresses interferences while they appear at the inputs 16 and 17. Counters 3 and 8, comparison circuit 7, node 13 of the control for odd parity (as main nodes) allow to control the correctness of the received information. The presence of signals True and False excludes the loss of information.

M la fegvtytya laiMiHd 15

Claims (2)

1. A SERIAL CODE CONVERTER TO PARALLEL, comprising a clock, a shift register, an output register, a control unit, a command register, wherein the information of the shift register is connected to the first information input of the converter, the input of the command register is the input of the converter mode setting, and the first output is connected with the first input of the control unit, the permitting output of which is connected to the control input of the output register, the output of which is the information output of the converter, about characterized in that, in order to increase the reliability of the operation, a comparison circuit is introduced into it, the first and second subtracting counters, the oddity control node, two OR elements, a trigger, an EXCLUSIVE OR element and a request signal shaper, the first and second information inputs of the converter through an EXCLUSIVE OR element is connected to the first input of the first OR element, the second input of which is connected to the output of the command register, and the output to the shift inputs of the shift register and the counting input of the first subtracting counter, reset input whose and the reset inputs of the trigger of the second subtracting counter and the oddity control unit are connected to the output of the second OR element, the first input of which is connected to the end of the control unit word, and the second input is the drive start input, the first information input of which is connected to the information input of the control unit oddness, the output of which is connected to the second input of the control unit, the third input of which is connected to the output of the comparison circuit, the first and second inputs of which are connected respectively to the output By the first and first outputs of the second subtracting counters, the output of the command register is connected to the control input of the shift register, the output of which is connected to the information input of the output register, the output of the clock generator is connected to the clock input of the request signal generator, the start input and gate input of which are connected respectively to the output trigger and the first output of the second subtracting counter, the second output of which is connected to the second input of the trigger and the fourth input of the control unit, the output of the driver the request signal is connected to the counting input of the second subtracting counter and is the output of the converter request, the third and fourth outputs of the control unit are the True and False outputs of the converter, the control unit contains a switch, SU „., 1193655 counter, eight AND elements, two NOT elements, a trigger and three delay elements, while the information inputs of the switch and the counter form the first input of the block, the information outputs of the counter are connected to the control inputs of the switch, the control input of the counter is connected to the output the first element And, the first input of which and the first input of the second element And are connected to the first output of the trigger, the output of the switch is connected to the second input of the second element And, the output of which is connected to the first input of the third element And, the output of which is enabled by the block output, the counter output is connected to the first input of the fourth element And, the output of which is connected to the second input of the first element And is the output. The end of the block word, the first inputs of the ninth and sixth elements And are connected respectively to the first and second outputs of the trigger, the first and the second inputs of which are connected respectively to the outputs of the seventh and eighth elements II, the second input of the fourth element And through the first delay element is connected to the output of the second delay element connected to the second the moves of the third, fifth and sixth elements AND, the outputs of the fifth and sixth elements AND are respectively the outputs of the True and False blocks, the fourth input of the block is connected to the input of the second delay element and through the third delay element with the first inputs of the seventh and eighth elements And, the second and third the inputs of the eighth element AND are connected to the second and third inputs of the block, through the first and second elements NOT connected to the second and third inputs of the seventh element I. 2. The converter according to claim 1, with the fact that the request signal generator comprises a decoder, a trigger, and an AND element, wherein, the clock, triggering, and gate inputs of the generator are connected to a group of decoder inputs , the first and second outputs of which are connected to the R and S inputs of the trigger, the output of which is connected to the first input of the And element, the second input and output of which are connected respectively to the clock input and the output of the driver. . 1 "·*.