SU1591194A1

SU1591194A1 - Data transceiver

Info

Publication number: SU1591194A1
Application number: SU884497890A
Authority: SU
Inventors: Sergej R Gostev; Vladimir E Pankin; Valentin M Shilkov
Original assignee: Sergej R Gostev; Vladimir E Pankin; Valentin M Shilkov
Priority date: 1988-10-24
Filing date: 1988-10-24
Publication date: 1990-09-07

Description

The invention relates to telecommunications And can be used when building communication networks of distributed computing systems for the organization of data exchange between parallel

and serial channels. The invention provides control of the least reliable units of the device, which increases the reliability of the device. The device contains serial and parallel communication channels 1 and 37, input line unit 2, input-output line unit 5, matching elements 3.6, receivers 4.7, transmitter 8, pulse generator 9, encoder 10, decoders 11.12, block 13 controls, triggers 14-19, elements AND 20 - 22, 27, 33, elements OR-NOT 23, 32, elements OR 24, 25, 29, element-AND-26, drivers 28, 31 pulses, counters 30, 34 pulse, element NO 35 and block 36 I / o.

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The invention relates to telecommunications and can be used when tweaking communication networks of distributed computing systems for organizing the exchange of data between parallel and serial channels.

The aim of the invention is to increase the reliability of the device.

The drawing shows a functional diagram of the device.

The scheme contains a serial communication channel 1, the input line unit 2, performed on the matching element 3 and the receiver 4, the input-output line unit 5, performed on the matching element 6, the receiver 7 and the transmitter 8, the pulse generator 9, the encoder 10, the second .11 and the first 12 address decoders, control unit 13, performed on the first - the sixth KZ-trigger 14-19, the first - the third element AND 20-22, the element OR-NOT 23, the first 25 and the second 26 elements OR, the AND element -NE 26 and the fourth element And 27, the first driver 28 pause pulses made n OR element 29 and the pulse counter 30, second pulse generator 31 records made on element 32 NOR ,, AND element 33, the pulse counter 34 and the NOT element 35, block 36 and the input-output channel 37 parallel connection.

In connection with the matching elements 3 and 6, for example, TIL2V pulse transformers, receivers 4 and 7 and transmitter-8 can be used on PRU and IPU ICs 445.081TU microcircuits. Coder-decoder 10 is made on micro. 588BG6 circuit, decoders 11 and 12 are made on 588BT1 and 1533ID4 microcircuits, input-output unit 36 is made on a 180-9BB1 microchip.

The device works as follows.

During the pause between messages there are no signals in the serial channel 1, as well as at the inputs and outputs of the elements 3 and 6 of the coordination, receivers 4 and 7 and the transmitter 8.

At the installation inputs of the driver

28 pulses (the inputs of the element OR 29 _y establish logical zero levels. This signal through the element OR

29 is transmitted to the reset input of the counter 30th allows the counting of pulses arriving at the counting input of the counter

30 from the generator 9. When the counter 30 counts the number of pulses corresponding to the minimum pause between messages, a pulse will appear at its output overflow, which will go to the installation inputs to “0” of the flip-flops 14-19, which will be set to the state “0”.

The signal levels at the outputs of the elements And 20-22 correspond to the logical. "0", and at the outputs of the elements ILINE '23, OR 24 and 25, AND-NOT 26 - logical "1". The installation inputs of the pulse shaper 31 receive signals of a logical "0", the output signal of a logical "1" of the element OR NOT 32 resets the counter 34.

From the output of the element NOT 35, the signal of logical "1" is fed to the input of the element I 33, allowing the passage of pulses from the output of the generator 9 to the counting input of the counter 34. But the counter 34 does not count because it is held in the zero state by a signal at the input reset. In this state of waiting, the device is before the start of data exchange via serial channel 1.

When the device transmits information to the serial channel 1 in the co-decoder 10 using the decoder 11 from the parallel channel 37, the information code of the transmitted word is recorded in the parallel code. When transmitting the Start signal through the parallel channel 37, the codec 10, synchronized by the generator 9, begins to generate two pulse sequences at the outputs; controlling the transmitter 8, from the outputs of which, via the matching element 6, the word is transmitted to the serial channel 1 in a sequential bipolar phase-shift keyed code.

For the formation of the transmitted word, the pulse sequences coming from the outputs of the coder-decoder 10 have the same repetition period and form. The meander, moreover, one sequence is shifted relative to the other by half the period. The duration of pulses is less than the minimum value of the pause between messages. The pulses from the outputs of the coder-decoder 10 are fed to the installation inputs of the driver 28 pulses, resetting the counter 30. The pause between the pulses6

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At the reset input of counter 30, there is less than the minimum pause between messages; therefore, counter 30 does not have time to count the number of pulses from the output of generator 9, corresponding to the pause between messages, and its output is constantly maintained by a logical “O” signal. The first pulses of the sequences from the outputs of the coder and decoder 10 set the triggers 18 and 19 to the logical state "1". At the output of the .22 element, the logic level “1” appears, which is fed to the third installation input of the pulse shaper 31 (the input of the element OR NOT 32). At the output of the element OR NOT 32, a logic level "0" is set, allowing the counter 34 to count the generator 9 pulses through the element. AND 33. Signals from the transmitter 8 outputs through the matching element 6 are transmitted to the inputs of the receiver 7, at the outputs of which the same two sequences of signals appear as at the inputs of the transmitter 8. The first pulses of these sequences set the triggers 16 and 17. to the state of logical 'Ί ".

A sequential bipolar phase-manipulated code transmitted over serial channel 1 by matching element 3 and receiver 4 is converted into the same pulse sequences as at the inputs of transmitter 8, setting triggers 14 and 15 to the logical "1" state. At the outputs of the elements And 20 and 21, OR 24 and .25. Levels of logical "1" are set,. and at the outputs of the elements OR NOT 23, AND-NOT 26 - the logical "0". The division factor of counter 34 is chosen so that after removing the reset input signal at the output of counter 34, a logical “1” signal appears after a period of time sufficient for the signals to pass through the circuits: transmitter 8 - matching element 6 receiver 7 - triggers 16 and 17 - I element 21 - IS-NOT 26 and transmitter 3 - matching element 6 - serial channel 1 - matching element 3 - receiver 4 - triggers 14 and 15 - AND element 20 - AND-NOT element 26. When the output 34 of the differential 34 appears, a logical · level from "0" to "G ¹ this differential is transmitted I'm on the input of the recording unit 36 vvo? Yes, the output, writing in it el. 1194

current information: from the outputs of the elements OR 24 and 25, I.20 and 21 - the level of logical "1", from the 'output of the element

5 OR NOT 23 - logical "0"'.Signals> logical "1" at the inputs of block 36 correspond to the following results of the control of the Device Blocks:

output element OR 24 - the absence of a short circuit in the serial channel 1;

the output of the element OR NOT 23 - control was carried out in the mode of reception from channel 1;

15 output element OR 25 - there is no information about the malfunction of the encoder-decoder 10 ("O" - malfunction);

output element And 20 '- received signals from both outputs of the receiver 4;

output element And 21 - received signals from both outputs of the receiver 7.

From the output element And 27, the signal is transmitted to the interrupt input of the block 36 I / o. If there are no operability signals from one of the receivers 4 and 7 or the encoder-decoder 10 at the inputs of the IS-NE element 26, the interrupt signal is transmitted through the block 36 to the interrupt bus of the parallel channel 37. When receiving the interrupt signal, the subscriber connected to channel 37 is address of the device using the decoder 12 addresses can read the information stored in

35 block 36 I / o n specify exactly which blocks failed. The signal logical "G ¹ coming from the output of the counter 34 is inverted by the element NOT 35 and transmitted to the input of the element AND

40-33, prohibiting the passage of the pulses of the generator 9 to the counting input of the counter 34.

The state of the device blocks changes during the transmission of 45 format to channel 1, all the time: - the device pauses between messages and goes into standby mode. In receive mode, the message from the serial channel of the element is 3 g; 6 matches and receivers 4 and 7 are converted into a sequence of pulses.From the outputs of receiver 7, signals are transmitted to the information inputs of the encoder-decoder 10, in which the reliability of the received word is monitored and transformed into a parallel form for subsequent transmission when accessing stroystvu on the parallel channel 37. With n receivers 4 outputs 7 po7

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pulse sequences are fed to the pause pulse shaper 28 and the control unit 13, which, together with the write pulse shaper 31, generate and record the results of the control of the device blocks as described above. A specific feature of monitoring in the modes of receiving and transmitting information is its execution on the first impulses of sequences received from the outputs of receivers 4 and 7 or to the inputs of transmitters 8. Therefore, monitoring can also be carried out when transmitting / receiving unreliable words. '

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Thus, the invention makes it possible to increase the reliability of the device over the control of blocks that are subject to failures and control during the exchange of data with subscribers, without allocating a special mode of self-control.

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Claims

Claim

A device for transmitting and receiving data, containing an input-output "linear unit", the inputs-outputs of which are connected to the serial communication channel, the first decoder, the outputs of which are connected to the corresponding address inputs of the input-output unit, the first trigger, the output of which is connected to the first input of the first element is And, the second to the fourth elements are And and the pulse generator ', characterized in that, in order to increase the reliability of the device, a coder-decoder, a second decoder, the second - sixth triggers, elements OR, e The OR-NOT element, the NAND element, the pulse shapers and the input line unit, the inputs of which are connected to the serial communication channel, the first and second outputs of the internal linear unit are connected respectively to the first and second setting inputs of the first $ pulse shaper and to the inputs installation in "1", respectively, the first and second triggers, the first and second outputs of the input-output line unit are connected respectively to the third and fourth installation inputs of the first pulse shaper, the first and second inf by the input inputs of the coder-decoder and the installation inputs to “1” of the third and fourth triggers, respectively, the first and second outputs of the co-decoder are connected respectively to the first and second inputs of the input-output line unit, the fifth and sixth installation inputs of the first shaper of the pulses and the installation inputs to - "1", respectively, of the fifth and sixth triggers, the output of the pulse generator is connected to the clock inputs of the encoder-decoder, the first and second pulse shapers, the output of the first pulse shaper is connected with the installation inputs in the "About" of the first - sixth triggers, the outputs of the second, third 'and fourth triggers are connected respectively to the second input of the first element And, the first and second inputs of the second element And, the output of the fifth trigger and connected to the first inputs of the third element And and the OR element -NO, the output of the sixth trigger is connected to the second inputs of the third element AI of the element OR NOT, the output of which is connected to the first inputs of the first, second elements OR and the first information input of the block. input-output, the output of the first element AND is connected to the second input of the first element OR, the first input of the NAND element, the first installation input of the second pulse shaper and the second information input of the I / O unit, the output of the second AND element connected to the second input of the NAND element, the second · The installation input of the second pulse shaper and the third information input of the I / O unit, the output of the third element And is connected to the second input of the second element OR and the third installation input of the second pulse shaper, output the output of the first OR element is connected to the fourth information input of the I / O unit, the output of the second OR element is connected to the fifth information input. the input of the I / O unit and the third input of the N – NE element, the output of which is connected to the second input of the fourth element AND, the output of the second decoder are connected to the corresponding address inputs of the encoder-decoder, the inputs-outputs of the encoder9 159 1194 10

the decoder, the first, the second deifratomi and fourth inputs-outputs of the

The moat and the I / O unit are properties.

responsibly first, second, three