SU690646A1 - Device for transmitting and receiving discrete information - Google Patents

Description

The invention relates to radio ..

A device for transmitting and receiving discrete information is known on the transmitting side. An address encoder whose input is connected to the first input of the AND element and an input of the counter whose output is connected to the second input of the AND element, the output of which is connected to the first input of the OR element through the first register message. , to the second input of which the output of the address coder is connected, and on the receiving side an address decoder, the input and output of which are connected respectively to the inputs of the first element And whose output is connected to the first input of the register The message, the second input of which is connected with the counter output, to the second input of which is connected an output of second AND gate having a first input coupled to an output address decoder, while the second input of the second AND gate supplies a clock signal ({.

However, in the known device the speed of information transfer is insufficient.

The purpose of the invention is to increase the speed of information transfer.

To do this, the device for transmitting and receiving discrete information contains, on the transmitting side, an address coder, the input of which is connected to the first input of the element I and the input of the counter, the output of which is connected to the second input of the element And whose output is connected to the first input through the first register the OR element, to the second input of which the output of the address coder is connected, and on the receiving side an address decoder, the input and output of which are connected respectively to the input of the first element AND, the output of which is connected to the first input register and a message, the second input of which is connected to the counter output, to the second input of which the output of the second element I is connected, the first input of which is connected to the output of the address decoder, and a clock signal is inputted to the second input of the second element I, a decoder unit is inserted on the transmitting side. the block of elements And the second register of the message, the outputs of which are connected to, the inputs of the block of elements AND, the outputs

which are connected to the additional inputs of the OR element, the additional inputs of the AND block are connected to the outputs of the decoder block, to the inputs of which the corresponding counter outputs are connected, an additional message register and a memory block are entered at the receiving side, the inputs of which are connected to the additional outputs of the address decoder whose output is connected to the corresponding input of the memory block, the outputs of which are connected to the inputs of the additional message register.

The drawing shows a structural electrical circuit of the proposed device.

The device contains on the transmitting side an address coder 1, element AND 2, counter 3, message register 4, element OR 5, block of descramblers b, block of elements AND 7, register of message 8, on the receiving side an address decoder 9, element AND Yu, message register 11, counter 12, element And 13, message register 14, memory block 15

The device works in the following way.

Suppose there are total N objects that need to send various messages, the volume of which is, for example, m binary symbols, and let the selected interval code contain N different code words (addresses) and there are K unused (always empty) intervals. In general . Then the message register 8 and message register 14 contain K cascades, and message register 4 and message register 11 contain (ha-K) cascades.

Before starting work, one of the address combinations or the object number is written to the address encoder 1, and 8 message registers 8 and 4 write the message code to this object.

If necessary, all these ta symbols can be pre-coded by some error-correcting code. As impulses arrive at the input, the address code from the coder 1 through the element OR 5 is passed to the output. At the same time, the same pulses go to the input of counter 3 and to the input of the AND 2 element, but do not pass to its output, because at the second input of the element And 2 there is no resolving potential. As the counter accumulates 3 pulses, the decoders from the decoders block. b recognize the free positions in the address code and send the corresponding signals to the block of elements AND 7, thereby allowing the passage of message symbols from the register of message 8 through the element OR 5 to the output. Thus, during the time of the address code, all K free will be recognized

positions in the code and in these places all K characters of information from message register-8 will be transmitted. After the end of the address-code. From counter 3, the resolving potential arrives at the element AND 2, and the remaining (t-K) characters of information from register x: message 4 through the element OR 5 arrive at the input.

In the initial O1 state, elements And 10 and 13 signals do not pass. The input signal enters the decoder of address 9 after input. After decoding the address, the signal from its output permits the passage of signals through elements 10, 13 and simultaneously enters the input of memory block 15. In memory block 15, position numbers are written in the address code where information symbols may be transmitted. The signal from the address decoder 9 contains the contents of these K positions in message register 14. Through the AND 10 element, the remaining (t-K) information characters are written into the message register 11. Through the element and 13, the counter 12 receives pulses from the generator with the same clock frequency as the entrance. After the counter 12 records the number (TK), the device stops working. The message registers 11 and 14 contain the received message.

Claims (1)

Invention Formula A device for transmitting and receiving discrete information containing on the transmitting side an address coder, the input of which is connected to the first input of the AND element and the input of the counter, the output of which is connected to the second input of the AND element, the output of which through the first message register is connected to the first input of the OR element the second input of which is connected to the output of the address coder, and on the receiving side an address decoder, the input and output of which are connected respectively to the inputs of the first element I, the output of which is connected to the first input of the message register, the second input of which is connected to the output of the counter, to the second input of which the output of the second element I is connected, the first input of which is connected to the output of the address decoder, and a clock signal is supplied to the second input of the second element And, in order to increase the transmission speed information, on the transmitter side, a block of decoders, a block of AND elements and a second message register are entered, the outputs of which are connected to the inputs of the block of AND elements whose output is connected to the additional inputs of the OR element, additional inputs of the block of elements and connected to the views of the block of decoders, to the inputs of which the corresponding counter outputs are connected, on the receiving side an additional message register and a memory block are entered, the inputs of which are connected to the additional outputs of the address decoder whose output is connected to the corresponding the input of the memory block whose outputs are connected to the inputs of the additional message register. . Sources of information taken into account in the examination 1, Venediktov MD et al., Asin-, chronic address communication systems. M., Connection 1968, pp.80-85 (prototype). Sxo5 addresses Tti Tfjxod I agree /