SU1229970A1 - Device for determining validity to transmission of binary information - Google Patents

Abstract

The invention relates to the measurement technique and m. used to assess the quality of transmission of discrete information in communication systems. The invention shortens the time for determining the validity. The device contains the input unit 1, unit 2 comparison.

Description

a decoder of 3 code combinations, a register of 4 shifts, a block of 5 half-adders, an electronic key 6, a block of synchronization 7, a driver of 8 pulses, three counters of 9-11 pulses (SI), two triggers 12, 13 and two electro-OR 14, 15. The goal is achieved by introducing the EL 15, SI 10, 11 and trigger 13. The El OR 14 is opened when the test text arrives and if there is phasing along the cycle. When the next piece of test text arrives, a pulse from the output of the decrypted output The invention relates to measurement technology and can be used to assess the quality of transmission of discrete information in communication systems.

The purpose of the invention is to reduce the time for determining the accuracy.

The drawing shows the structural electrical circuit of the device for determining the reliability of transmission of binary information.

The device contains an input block of a comparison block 2, a decoder of 3 code combinations, a shift register 4, a block of half combiners, an electronic key 6, a block of synchronization 7, a former 8 of pulses., The first 9, the second 10 and the third 11 pulse counters, the first 12 and second 13 triggers and first 14 and second 15 elements OR.

The device works in the following 11p1 fashion.

In the initial state, the first trigger 12 is in such a position that the electronic key 6 switches the shift register 4 input with the output of the input unit 1, and the third pulse counter 11 is in the pulse counting mode, coming from the pulse generator 8 output. The second trigger 13 is in such a state that the first element OR 14 is closed and the counters 9 and 10 of the pulses are in the counting mode. When writing N characters of the test text to the 4-shift register, where N

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Step 3 overturns trigger 13 into a loop-free phasing state. SI 9, 10 check for phasing. If the phasing is not violated, the flip-flop 13 overturns and the confidence measurement process is performed. The element-wise phasing of the received and generated symbols is performed by the synchronization unit 7. The short pulses necessary for the operation of the comparison unit 2 are generated by means of pulse generator 8. 1 sludge.

the length of the shift register 4, at the output of the third counter of 11 pulses, with a recalculation factor equal to N, a pulse is generated that overturns the trigger 12. In this case, the trigger 12 switches the electronic key 6 so that the shift register 4 turns out to be connected to the output of block 5 Simultaneously, the pulse counter 11 is blocked. In this position, the electronic key 6, block 5, and the shift register 4, which are the test text sensor, are filled with a test text that is in sync with the received one. In the case of writing to the 4-shift register of one or several mistakenly received characters, the local test text will not be in phase with the received one.

To detect synphase or. cycle skews, a pulse counter 9 is used with a conversion factor L, a pulse counter tO. the conversion factor and the trigger 13. Pulse counter 9 counts the error pulses from the output of the comparison unit 2 when the generated test text does not match the received one. Pulse counter 10 counts clock pulses. If the number of error pulses is more than L less than a check per M clock intervals, then a decision is made to decadent the cycle, trigger 12 is reversed to its original state and the process

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synchronicity repeats. If the number of errors is less than L, then a pulse formed at the input of the pulse counter 10 pulses the trigger 13 into the state of synchronization on the cycle. In this case, the potential at the inverse output of flip-flop 13 through the element OR 15 blocks the counters 9 and 10 pulses. The first element OR 14 opens and the pulses determining the reliability of the received information are output from the unit 2 of the comparison to the output of the device.

When transmitting test text segments in the information flow, the decoder of code combinations 3 generates a pulse at its first output, the beginning of which coincides with the beginning of the test text segment, and the end with the end of the test text. At the second output of the decoder 3 code combinations, a pulse is formed corresponding to the beginning of the test text.

Thus, the first element OR 14 turns out to be open only when the test text segment arrives and if there is a loop phasing. When the next piece of the test text arrives, the pulse generated at the second output of the decoder 3 code combinations flips the trigger 13 into the no-phasing state the cycle and with the help of counters 9 and 10 pulses are checked for phasing. If the phasing is not violated, the trigger 13 overturns and the confidence measurement process is performed. AT

If phasing is violated, phasing is performed again. The element-wise phasing of the received and generated symbols is performed using the synchronization unit 7. The short pulses necessary for the operation of the comparator unit 2 are generated by means of an impulse generator 8.

Claims (1)

Invention Formula A device for determining the reliability of transmission of binary information, comprising a codeword decoder, a block of half adders, VNIIPI Order 2D61 / 59 Random polygons pr-tie, Uzhgorod, st. Project, 4 ten 15 2299704 first OR element and serially connected input block, synchronization block, pulse shaper, compare block, first pulse counter 5, first trigger, electronic key and shift register, the first output of which is connected to the second input of the compare block and the corresponding code decoder input, others the corresponding inputs of which are connected to the corresponding output of the shift register, the other corresponding outputs of which are connected to the corresponding inputs of the block of half-adders, the input synchronization and the shift register is connected to the output of the synchronization unit, the output of the half-adders unit is connected to the second input of the electronic key, the third input of which is connected to the third input of the comparison unit and the output of the input unit whose input is the device input, the first output of the code decoder code combinations connected to the first input of the first element OR, which differs in that, in order to reduce the time for determining the reliability, the second element OR, the second and third pulse counters and the second trigger, direct output to torogo connected to second input of first OR inverse output is connected to the first input of the second OR gate having a first input connected to a second installation decoder output codewords, the second set input coupled to a second input of the second OR gate and the output 20 25 thirty 35 the first counter, the reset input is connected to the third input of the second element OR to the output of the second pulse counter, the installation input of which is connected to the installation input of the first pulse counter and to the output of the second OR element, and the counting input is connected to the output of the third pulse generator The installation input of which is connected to the output of the first trigger, the installation input of which is connected to the output of the third counter, the output of the comparison unit is connected to the third input of the first element LEE, whose output is the output device. Circulation 624 Subscription