SU1336254A1 - System for correcting errors in transmission of n-position code words - Google Patents

Abstract

The invention relates to computing. Its use in information transmission systems, as well as for checking multi-wire communication lines, allows to increase the reliability of information transmission by correcting double errors. The transmitting part 1 of the system contains a register 3, a group of 4 controlled inverters and a control unit 8. The receiving part 2 contains a register 9, a group of 10 controlled inverters and an error detection unit 14. By introducing into each part of the system a counter 7 (13), a converter 6 (12) of a code and a group 5 (11) of controlled inverters, it is possible to correct double errors by double inverting the bits of the transmitted code word according to a certain rule. 1 hp f-ly, 6 ill. 2 tab. with co 05 tsD 01 4;

Description

The invention relates to the field of computer technology and can be used in information transmission systems, as well as for checking system buses or communication lines.

The purpose of the invention is to increase the reliability of the transmitted information by correcting double errors.

FIG. 1 shows a functional system diagram; in fig. 2 is a control block diagram; in fig. 3 shows an exemplary embodiment of an error detection block; in fig. 4- 6 are diagrams illustrating the work of this topic, respectively, in the absence of errors, in the presence of a corrected error and in the case of a failure.

The system for correcting errors in the transmission of N-bit code words consists of transmitting and receiving parts 1 and 2. Transmitting part 1 contains a register 3, the first and second groups 4 and 5 of controlled inverters, a code converter 6, a counter 7 and a block 8 controls

The receiving part 2 contains the register 9, the first and second groups of 10 and 11 controlled inverters, a code converter 12, a counter 13, and an error detection unit 14. The transmitters, and the receiving parts 1 and 2 are interconnected by the first - fifth lines 15-19 of communication. The system has information inputs 20, synchronous input 21 ,. information outputs 22-24.

Registers 3 and 9 are parallel N-bit registers.

Controlled inverters of groups 4, 5, 10, 11 can be performed on modulo-two adders or as in a known device.

Converters 6 and 12 codes are identical in accordance with the table. 1 truth (for example, in the form of serially connected decoder and encoder).

Table 1

The control unit 8 (FIG. 2) is executed on the trigger 25, the counter 26, the decoder 27, the AND-NE element 28, the AND 29 element, the OR-NOT 30 element and has a clock input 31, the first and second control inputs 32 and 33, the first - the third outputs 34-36.

The decoder 27 works in accordance with the table. 2 truths.

table 2

Input code (bit 1, 2)

Exit code (bit 0,1,2)

00 10 01 11

100 001 011 00.0

0

five

0

five

five

The error detection unit 14 (FIG. 3) performs a convolution of the modulo four codeword and is performed on modulators 37 modulo four, modulators 38 modulo two and OR 39 element. Modulators 37 modulo four can be performed on AND 40 and adders

41 modulo two. Block 14 has inputs

42 and exit 43.

FIG. 4-6 marked;

a - clock pulses at the input 21;

b, c - signals at the outputs of the first and second bits of the counter 26 of the control unit 8;

g, d - clock pulses at the first and second outputs of control unit 8;

e is the signal at the synchronization input of the trigger 25 of the control unit 8;

W is the signal at the output of the error detection unit 14;

3 signal at the trigger output

25 control unit 8;

and a signal at the third output of the control unit 8;

k, l, m, n - signals at the outputs of zero - third bits of the counter 7 or 13;

o- signal failure at exit 23

or 24.

The system for correcting errors in the transmission of N-bit codewords works as follows.

When an error-free transmission, the sync pulse 21 of the system receives sync pulses (Fig. 4a), which in the control unit 8 generate system clock pulses. At the beginning of each clock cycle, a first clock pulse is generated at the first output 35 of block 8 (Fig. 4d). arriving at the control input of register 3 and the zeroing inputs of counters 7 and 13. On this impulse, register 3 receives an N-bit binary code from information inputs 20, and counters 7 and 8 nullify. On the zero states of the counters 7 and 13 at the outputs of the corresponding converters 6 and 12 and

The outputs of groups 5 and 11 form zero potentials. The binary code is transmitted from the outputs of register 3 through a group of 4 controlled inverters to the first communication line without change, i.e. in the forward code, and then from the communication line through a group of 10 controlled inverters, without changing to the information inputs of the register 9 and to the inputs of the error detection unit 14.

If the code is transmitted without error, i.e. there is no signal at output 43 of block 14 and at the first control, input 32 of control block 8, the polling pulse at output 36 of block 8 is not generated and the state of counters 7 and 13 does not change. A second clock pulse at the second output 35 of block 8 (Fig. 4e), arriving via the communication line 18 to the control input of the register 9, is written to the register 9 of the transmitted code word. Information from the outputs of the registers 9 is transmitted to the information outputs 22 of the system.

In the presence of a corrected error, the process of correcting an error consists of repeating the transmission with a sequential inversion of groups of bits of the source code.

If an error signal is generated at the output 43 of the unit 14 in a certain cycle (FIG. 5g), the first control input 32 of the control unit 8 is fed through the communication line 16, then the output 36 of the unit 8 generates a polling pulse (FIG. 5i), This pulse, which arrives at the counting inputs of counters 7 and 13, modifies the state of these counters by plus one and forms the corresponding potentials on the code outputs of the counters (Fig. 5k). After modifying the states of counters 7 and 13, the converters 6 and 12 produce correspondingly the corresponding code, and at the outputs of groups 5 and 11 a corresponding transcoding parameter is generated, which is fed to the control inputs of the corresponding controlled inverters of groups 4 and 10.

The source code bits corresponding to the unit bits of the transcoding parameter are inverted. Converted in accordance with the conversion code, the binary code from the output of the group of 4 elements is transmitted via the communication line 15 to the information inputs of the controlled inverters of group 10, from whose outputs the already restored original binary code is transmitted to the information inputs of the block 14, If the control input 32 of the block When the control signal stops forming an error signal, the polling pulse at the output 36 (FIG. 5i) will be single at this time, after which at the output 35 of the control unit 8 a second clock pulse is generated (FIG. 5d). On the second clock pulse, coming through the communication line 18 to the controlled input of the register 9,

0

A corrected codeword is received in register 9.

During system operation, errors may occur that initially appear as uncorrectable (an error signal is generated both when transmitting the forward information code and when transmitting a return code), but for some group of invertible bits of the source code, the errors become corrected, for example when transmitting a code with values of 01 or 10 in closing connections or connections with a break.

If such an error occurs during a certain cycle, an error signal is generated at the output 43 of block 14 during the entire time that the error is non-correcting. The error signal is fed via link 16 to control input 32 of control unit 8. According to the first polling pulse generated at the output 36 of the control unit 8,

0, a modification is made to the plus state unit of the counters 7 and 13 and the generation at the outputs of groups 5 and 11 of the transcoding parameter, which sets the inverse of all bits of the source code. If the error signal

r continues to flow to the control input 32 of the control unit 8, then the output 36 of the unit 8 forms a second polling pulse, according to which a modification is made to the plus state unit of the counters 7 and 13 and the output of the groups 5 and 11 is generated

0 transcoding parameter specifying the inverse of the bits of the source code belonging to the first group. With each successive polling pulse, the state of the counters 7 and 13 is modified by plus one. As a result, the system produces a sequential formation of the forward and inverse codes of the transcoding parameter, given in 1, its inversion of the bits of the corresponding group. The choice of the direct or inverse code of the transcoding parameter is made according to the value of the signal at the low-order output.

0 counters 7 and 13, arriving at the control. The main inputs of the controlled inverters in groups 5 and 1 1.

The signals at the outputs of the higher bits of counters 7 and 13 determine the code group

5 inverting bits. If, after the next interrogation pulse, the modifying state of the counters 7 and 13 by plus one, the output 43 of block 14 and control input 32 of block 8 stops generating an error signal, this pulse of poll will be the last at the output 36 of control block 8 in the current cycle . A second clock pulse at the second output 35 of the unit 8, which is fed through the communication line 18 to the control input of the register 9, records the register 9 of the corrected code word, which is transmitted to the information outputs 22 of the system.

If the error continues to persist and is non-controlling during a time interval exceeding the threshold time (in the device implementation under consideration, the threshold time is Cs 1 t, where t is the period of the sync pulses on the synchronous input 2 of the system, Ketch is the counting factor of counters 7 and 13) then the first and second control outputs 23 and 24 of the system from the overflow outputs of the corresponding counters 7 and 13 are transmitted the failure signals (Fig. 6). In this case, the generation of polling pulses at the output 36 of the block 8 is stopped, and at the output 35 the formation of the second clock pulse is not performed, since the result of the transmission of the binary code is unreliable. With the long presence of an error signal at the control input 32 of block 8 (Fig. 6g), the setting of the trigger 25 is confirmed for each polling pulse, and the response of element 28 is NOT prohibited by the potential from the zero trigger 25. If the error signal is present for a time the threshold time, the counter 7 (13) is modified before overflow, the output of the overflow of counter 7 (13) generates a failure signal arriving at the output 23 (24) and the third input of the control unit 8, where it causes reset of the trigger 25. At the same time, the operation lock is released and AND-NO element 28 and the next pulse from the output of this element 26 is modified on the state of the counter plus one. By the unit state of the bits of the counter 26, the decoder 27 produces a pulse at the second (last) output.

If the error signal continues to be present after the threshold time has elapsed, the generation of the second clock pulse by element 30 is blocked.

The system can be simpler to perform if the counter 13 is deleted at the receiving side 2, and the converter 12 inputs are connected by the corresponding line to the outputs of the counter 7 of the transmitting side I. The simplification can be even greater if at the receiving side 2 the converter 12 is deleted The second group 11 controlled inverters, and the control inputs of the controlled inverters of the first group 10 are connected via a communication line to the outputs of the corresponding controlled inverters of the second group 5 of the transmitting side 1. However, at each This simplification increases the number of connections in the communication line, which can reduce the immunity of these options.

Thus, in the proposed system, double errors are corrected, caused by the breakage of two connections or their closure between themselves.

Claims (2)

1. A system for correcting errors when transmitting CU-bit code words, contains five 0 five 0 five 0 five 0 five register on the transmitting side; V outputs of which are connected to information inputs of the same name controlled inverters of the nerve group, a control unit whose clock input is the system sync input, information inputs of the register are information inputs of the system, outputs of controlled first inverters are connected to the inputs of the first communication line, on the receiving side, the first group of N controlled inverters, the outputs of which are connected to the corresponding information inputs of the regi (gpa, an error detection unit, the information inputs of the controlled inverters of the first group are connected to the outputs of the first communication line, the outputs of the register are information outputs of the system, the output of the error detection unit through the second communication line is connected to the first control input of the control unit, characterized in that the reliability of the transmitted information due to the correction of double errors; a code converter, a second group of controlled inverters and a counter, low-order output are entered on the transmitting and receiving sides of the system It is connected to the control inputs of the controlled inverters of the second group, the outputs of which are connected to the control inputs of the same name controlled inverters of the first group, the outputs of the remaining bits of the counter are connected to the inputs of the code converter, the outputs of which are connected to the information inputs of the corresponding controlled inverters of the second group, the first output of the control unit is connected directly to the control input of the register and the zeroing input of the counter of the transmitting side and through a third communication line to the zeroing input the receiving terminal side, the second output of the control unit through the fourth communication line is connected to the control input of the receiving side register, the third output of the control unit is connected directly to the counting input of the counter of the transmitting side and through the fifth communication line to the counting input of the counter of the receiving side, the inputs of the block error detection is connected to the outputs of the corresponding controlled inverters of the first group of the receiving side, the overflow output of the counter of the transmitting side is connected to the second control input of the control unit tim and is the first control output of the system, the overflow output of the counter at the receiving side is a second output of the control system. 2. The system of claim 1, wherein the control unit is executed on a trigger, a counter, a decryptor, an AND element, an OR-NOT element and an AND-NO element whose output is connected to a counter input of the counter, whose outputs are connected to information inputs zero output is the first output of the control unit, the output of the first discharge of the decoder is connected to the first input of the AND element and the trigger synchronization input, the output of the second discharge of the decoder is connected to the first input of the OR NOT element, inverse output of the trigger connector The first input of the NAND element, the second input of which and the resolution enable input of the decoder record are combined and are the clock input of the control unit, the second inputs of the AND and OR NO elements and the trigger information input are combined and are the first control input of the control unit, the input the flush trigger is the second control input of the control unit, the output of the OR-NOT element and the output of the AND element are the second and third outputs of the control unit, respectively. 2 s I b 6 y d P P l fig L Beat Tact fo.6 Compiled by O. Revinsky Editor N. EgorovaTehred I. VeresKorrektor E. Roshko Order 3815/57 Circulation 901Signature VNIIPI USSR State Committee, but inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4