SU1322378A1 - Device for checking m groups of registers - Google Patents

Abstract

The invention relates to computing and can be used for test control of shift registers. The aim of the invention is to increase the reliability of control due to the localization of faulty registers. For this purpose, a group of additional adders modulo two is entered into the device, so that the total number of adders equals the number of controlled registers. The control is carried out by comparing the codes at the outputs of the controlled and control registers. 2 Il. oo to th 00 00

Description

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The invention relates to computing and can be used for test control of shift registers.

The purpose of the invention is the verification of control due to the localization of faulty registers.

FIG. Figures 1 and 2 show the block diagram of the monitoring device, as well as the controlled shift registers.

All controlled registers of 1 lena per group of groups 1.1.1 1.1 and 1.2.1 - ..., 1.t .. - .m.K. Each group of controlled registers of the same size. All registers are triple devices.

The device for control contains t control shift registers 2.1-2.t, t groups of adders modulo two 3.1.1 3.1.U, 3.2.1 3.2.N 3.sh. 1 W.b. Each group of adders for an m.t.u two consists of an adder modulo two and a group of additional adders modulo two. FIG. 1 and 2 also show clock in. 4 device output, input D) control information of the device, control outputs 6.1.1 6.1.a. D) .2.1 D) .2. “.... ..., f.nt. 6.ShK device.

Consider the operation of the device on a specific example. At () m, c.ie will be given with the initial data) 1m.

Suppose there are three controllable shift registers: two registers 1.1.1 and 1.1.2 with four digits, two registers 1.2.1 and 1.2.2 but inecTb bits and two registers 1.3.1 and 1.3.2 but oct. Dov. The device contains a control register 2.1, consisting of four bits, one control register 2.2 and 2.3, consisting of two bits, the memory of adders modulo two 3.1.1, 3.1.2. 3.2.1, 3.2.2, 3.3.1, 3.3.2 each with two and one output output,, 1 ment (supports.

Before the beginning of pa6oTi) i, the co-controlled registers and the device q, 1 coptro, 1I must be set, in the beginning and in my state. This can be done several1) Kimi ways. According to the first} of them, well.) E start, 1H1e state is set by supplying T ooT-compliant control, 1 second signal to the inputs of the resetting co-transistor and co-transceiver registers, second method

1322378

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involves setting any initial state by writing from the input 5 of an eight-bit sequential code device to the monitored and control registers of the shift pulses coming from the input 4 of the device.

In the absence of faults in the monitored registers, the inputs of all adders 3 modulo two receive the same codes, so the signals at the outputs 6 are equal to zero.

Let, as a result of a failure in register 1.3.1, the signal at its output received an incorrect value “O, although the signal at its input“ 1. Then, at the output of 6.3.1 devices, a signal "appears at the moment the modulo two 3.3.1 of the wrong signal value arrives at the second input.

. Similarly, failures are found in other controlled registers.

Claims (1)

Invention Formula A device for controlling groups of registers, containing modulo-2 adders and t control registers, the sending informational outputs of which are connected to the first inputs of the corresponding modulo-two adders, and the clock inputs are the clock input of the device, different that, in order to increase the reliability of the counter, due to the localization of faulty registers, it contains m groups of additional, 1 modul double adders, with the first inputs of modulators two two of each group are connected to a sequence; The output of the corresponding control is: the first pei-ister, the second inputs of all modulo-two adders are the control (), the first inputs of the device, and the outputs are the control,: the first outputs of the device The first control register is the input of the control information of the device, and the next 1) 1st information input is the first one for the next control register (. ()) with the previous information output of the previous control register. 45