SU1434542A1 - Counter - Google Patents

Description

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four

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The invention relates to automation and computing and can be used to implement technical means in these areas,

The purpose of the invention is to increase the accuracy of the counters, c.

; The goal is achieved by ckeT introducing into the counter new Q | yktivnyh signs, providing after several cycles of control - 1 adan of the counter with an odd module and a forbidden state.

} The drawing shows a structural 15 with | heme of the proposed counter.

The counter contains a 1-shift P-bit register, with bits .1.1 1.5. The first element is H 2, with multiple inputs. the element AND 3, the second element AND 4, the ele-20 r-isHT OR 5, the input control unit 6, the installation bus 7 and the control bus 8.

 The first and second inputs and the output of the element And 2 are connected, respectively, 4 inv.aturn outputs of the last 25

1 gap of 1.5, the penultimate bit of 1.4 and with no 17Ormed input of the first ij-o bit 1.1 of the 1 shift register, -i-aKToBMe and setting the inputs of each bit 1.1 - 1.5 of which Jq

(respectively, from the input 7 of the installation, the control bus is connected to the output of ifieHTa OR 5, the first and second inputs | of which are connected respectively to the output of the I-I element And 3 and the And 4 terminal of the fifth and second inputs are connected respectively to the direct jitaMn output of the first bit 1.1 and the last bit 1.5 of the 1 shift register, iy-. The first outputs of the first bit 1.1 and the last bit 1.5 of which are connected respectively to the first and second inputs of the IZ element, the rest of the inputs of which, where P | ,, | To П-2, connected, respectively, with the pr - Prym outputs of bits 1.4 - 1.2, starting with the penultimate bit 1.4 of register 1 (indicates rounding to the nearest integer with a disadvantage),

The estimator works in the following way.

Before starting operation, register 1 is set to the state of 00 liters; About the signal on the bus 7, When the receipt of the clock signals on the bus 6

45

50

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Q

five

0

five

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five

five

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; Modulo their conversion (2P-1). If as a result of a fault in the counter, a forbidden state arises, then through the number of cycles that do not exceed (2P-1), the bus 8 is in the range of 1, which indicates a counter error.

By increasing the number of inputs K, the average delay time of the error detection signal can be reduced.

In the proposed counter, any failure in the forbidden states will be detected with a probability of 2 - (2P - - 1) / 2. The signal generated on bus 8 control can be used to correct a counter for a set of allowed codes, for example, by using a signal on bus 8 to set the bits of register 1 to one of the allowed states on the additional setup inputs,.

Claims (1)

1 claims The counter containing the input bus, installation bus, the P-bit shift register and the first, the element I, the first, second inputs and the output of which are connected respectively to the inverse outputs of the last and next to last bits and to the information input of the first bit of the shift register, The clock and installation inputs of each of the bits of which are connected respectively with the input bus and with the installation bus, about one and the same. In order to improve the reliability of the operation, a second AND element, a multiple-input AND element, an OR element and a control bus, which is connected to the output of the OR element, the first and second inputs of which are connected, are introduced into it. respectively with the output of the multi-input element I and with the output of the second element I, the first and second inputs of which are connected respectively to the direct outputs of the first and last bits of the shift register, the inverse outputs of the first and last bits of which are connected respectively to the first and a second multi-input AND gate inputs, the other inputs of which K, where K 3 P {i-2, are connected respectively to the outputs straight bits, starting with the penultimate shift register.