SU1525884A1 - Shaper of clock pulses - Google Patents

Abstract

The invention can be used in devices of automation and computing. The purpose of the invention is to increase the reliability of operation - achieved by introducing a valve 3, the inputs of which are connected to the inverse outputs of the flip-flops 1.1-1.N, and connecting the direct output of the flip-flop 1.1 to the reset inputs from the third to N + 1/2 of the flip-flops, if N-odd, and from the third to N + 2/2-nd, if N-even. The device also contains a valve 2 and an input bus 4. 3 Il.

Description

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The invention relates to a pulse technique and can be used in automation and computing. The purpose of the invention is to increase the reliability of operation.

Figure 1 shows the electrical block diagram of the device; 2 shows a graph of the operation of a pyrazd device; in FIG. 3, tables of states of false cycles of operation of the device.

The clock pulse shaper contains n flip-flops 1.1, 1.2, ..., 1.P, the first gate 2 (of the OR type), the second gate 3 (of the I type) and the 4 sync pulse bus, which is connected to the synchronization inputs of all the triggers. The information inputs of each subsequent trigger (1.2 relative to 1.1) are connected to the direct output of the previous one. The direct output of the nth trigger 1.n is connected to the first input of the first ventilator TSH1Ya 2, the output of which is connected to the information input of the first trigger 1.1. The second input of the first valve 2 is connected to the output of the second valve 3, the corresponding inputs of which are connected to the inverse outputs of the corresponding flip-flops 1.1, ... 1.p. In addition, the direct output of the first trigger 1.1 is connected to the inputs of the installation in the zero state from the third to the i-th trigger 1.3, ..., li, where 1 (n + 1) / 2 at n-odd and i () / 2 for n-even.

The clock driver operates in the following way.

Upon receipt of the sync inputs of the trigger 1.1, ..., 1.P sync pulses with 11ДНЫ 4 at the outputs of these triggers for 1, a running chart of the running unit type is generated. The pulse duration at each output is equal to the duration of the sync pulse period. With the arrival of each sync pulse, the single state of one trigger ends and begins in the next trigger. The unit state of the last trigger 1.n is transmitted through valve 2 to the information input of the first trigger 1.1. Thus, the work cycle is not interrupted.

In the states of the flip-flops 1.1, "1.P. All zeros at the inputs of the valve 3 receive single levels from the inverse outputs of these flip-flops. The output of the valve 3 is a single signal, which through the valve 2 post0

reports on trigger information entry 1.1. With the arrival of sync pulses from the bus 4, a single level appears at the output of trigger 1.1 and moves further along the chain of triggers with the arrival of subsequent sync pulses.

The state of all units with the arrival of clock pulses from tire 4 is replaced

the state is all zeros, the exit from which to the operating mode is indicated. When false (redundant) single states appear in the triggers, these states are automatically brought to the workers.

 Thus, the duty cycle at failure is restored by itself.

To illustrate this, consider the operation of the ring meter on which this device is based. The switching graph of the ring counter on 1K-triggers, for example, five-bit ones, is shown in Fig.2. The operation schedule consists of three subgraphs (fig. 2a, b, c), of which only 5

ring subgraph (Fig.2A). For each working state of the subgraph, there are three false conditions, of which the ring counter enters the duty cycle independently, equipment for the output from these states is not required. It is necessary to provide only the output of the ring counter from the states of the ring of the subgraph (Fig. 26). To construct a ring counter from false states, it is necessary to know the number of false cycles and at least one of the stable states in each cycle.

In case of false switchings, there are no stable states characterized by the presence of at least two single signals in adjacent bits. Therefore, the number of false switching cycles can be determined as follows. A table is made (Fig. 3) in which the number of columns is equal to the Number of bits of the counter. In the rows it is necessary to place single signals sequentially through 1,

0 2, 3, etc. zero and their combinations in such a way that there are no two unit levels in the first and last column at the same time. Of the set of lines that differ only in the sequence of units, and not the number of zeros between them (for example, 101000 and 100010), one line should be left. Then the number of lines gives

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the number of false cycles, and the values of the table cells gives one of the states of the false cycle. The tables shown in figure 3 show that for n 4, 5, 6, 7 and 8, the number of false cycles, respectively, is 1,1,2,3 and 6.

Further, the wire analysis of the tables, it can be noted that for the ring counter with the number of bits (triggers) n 4 and p 5 it is necessary to eliminate the simultaneous presence of units in the first and third bits, for n 6 in the first, third and fourth bits .

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For a ring counter with step 8, in the presence of a unit in the first discharge, it is necessary to eliminate single states in the third, fourth, and fifth bits.

In the general case, with the number of bits n, it is necessary to eliminate the simultaneous presence of units in the first, third, etc. bit dah to (n + 1) / 2 nd bit inclusive with n-odd or up to (n + 2) / 2-th bit inclusive with n-even. In this device for

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Claims (1)

This uses the inputs for setting the triggers to the zero state. Invention Formula A clock pulse generator containing n triggers, the synchronization inputs of which are connected to the clock bus, the information input of each subsequent trigger is connected to the forward output of the previous one, and the first gate, the first input of which is connected to the forward output of the nth trigger, which distinguishes that, in order to improve the reliability of operation 5, a second valve was inserted into it, the corresponding inputs of which are connected to the inverse outputs of the corresponding triggers, the output to the second input of the first valve, the output of which connected to the information input of the first trigger, the direct output of which is connected to the inputs of the installation in the zero state, from the third to (n + 1) / 2nd triggers, if n is odd, and from the third to (n + 2) / 2- of triggers, if n is even. 0 five Fi.Z