SU1684918A1 - Simulator of interferences - Google Patents

Abstract

The invention relates to a pulse technique and can be used in test equipment. The purpose of the invention is to improve the accuracy of interference simulation by introducing into the interference simulator a generator 2 pulses, a noise generator 3, a counter 6 pulses, a decoder 9, triggers 12, 13, 14 and 15, a comparison block 16, elements OR 17 18, 19, 20, 21 and 22, element 24, key 25 of the first and second tires 26 and 27 of control, the formation of new functional links. The simulator contains a generator of 1 clock pulses, counters 4.5 and 7 pulses decoders 8 and 10, trigger 11, element 23 1 il.

Description

The invention relates to a pulsed technique and can be used in instrumentation technology.

The purpose of the invention is to improve the accuracy of noise simulation.

The drawing shows a structural electrical interference simulator circuit.

Interference simulator contains 1 clock pulse generator, 2 pulse generator, 3 interference generator, first 4. second 5, fourth 6 and third 7 pulse counters, first 8, third 9 and second 10 decrypt ary, first 11, fifth 12, second 13, third 14 and fourth 15 triggers, block 16 compare, first 17, fourth 18. third 19, fifth 20, sixth 21 and second 22 elements OR, first 23 and second 24 elements AND, key 25, first 26 control bus and a second 27 control bus connected to the input of the fifth trigger, the output of which is connected to the second input of the first element OR 17, to the first the input of the fourth element OR

18 and with the second input of the fourth trigger 15, the first output of which is connected to the second input of the second element AND 24, the output of which is connected to the first input of the key 25, the second input of which is connected to the output of the interference generator 3. The output of the clock generator 1 is connected to the synchronization input of the first trigger 12, to the second input of the first element 23 and to the synchronization input of the first counter of 4 pulses, the outputs of which are connected to the inputs of the first decoder 8, the output of which is connected to the second input of the second trigger 13 and the second input of the sixth element OR 21, the first input of which is connected to the output of the first element AND 23, the first input of which is connected to the output of the first trigger 11, to the synchronization input of the third counter of 7 pulses and to the second input the fourth element of the LIA 18. The output is connected to a third product of the second flip-flop 13, a first input of m LLP 00

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element OR 20, with the third input of the third trigger 14 and with the synchronization input of the second counter of 5 pulses, the outputs of which are connected to the second group of inputs of the comparison unit 16 and the inputs of the third decoder 9, the output of which is connected to the first input of the third trigger

14, the output of which is connected to the first input of the second element OR 22 and to the input of the first trigger 11, the synchronization input of which is connected to the output of the sixth element OR 21. The output of the pulse generator 2 is connected to the first input of the fourth pulse counter 6, the outputs of which are connected to the first group of inputs comparison unit 16, the output of which is connected to the control input of the second pulse counter 5, to the second input of the third trigger 14 and to the first input of the second trigger 13. The second output of which is connected to the second input of the fifth element OR 20, the stroke of which is connected to the second input of the fourth counter 6 pulses and to the second input of the second element OR 22, the output of which is connected to the first input of the second element AND 24. The outputs of the third counter 7 of pulses are connected to the inputs of the second decoder 10, the output of which is connected to the second input of the third element OR 19, the first input and output of which are connected respectively to the first control bus 26 and to the first input of the fourth flip-flop.

15, the second output of which is connected to the installation input of the third counter of 7 pulses. The first output of the second trigger 13 is connected to the first input of the first element OR 17, the output of which is connected to the input of the first counter of 4 pulses.

Interference simulator works as follows.

The pulse counter 4 counts the duration of the emission of interference, and the pulse counter 6 counts the duration of the pauses between them. The duration of the pauses is set by the counter 5 pulses in such a way that each next pause is greater than the previous one for the duration of the pulse period from the output of the generator 2 pulses. The length of the pauses starts from zero and ends with the maximum value determined by the decoder 9. After the radiation following the maximum pause, the cycle of the emissions repeats. The number of cycles is counted by the counter 7 pulses, and after their number reaches the maximum value determined by the decoder 10, the trigger 15 stops the operation of the interference simulator.

After switching on the noise simulator, a zero signal is sent to the first control bus 26, which through the third element OR 19 sets the trigger 15 to the initial (zero) state. In this state, the trigger 15 zeroes the pulse counter 7 and closes the key 25 through the second element 24. After this, the generator is turned on.

3 noise, but its signals will not pass to the output of the interference simulator, since the key 25 is closed. After turning on the simulator

0 the generator starts with 1 clock pulses and the generator 2 pulses. The pulses of the generator 1 clock pulses are fed to the synchronization input of the counter

4 pulses and trigger trigger input 5 12. A trigger signal is supplied to the second control bus 27, which is the information input of trigger 12. In order to prevent premature radiation, a trigger signal is given after

0 feeds to the first bus 26 of the control signal zero. On the trigger signal trigger 12 generates a signal of the initial installation. This signal is fed to the synchronization input of the counter 5 pulses through

5 element OR 18, to the input of the capacitor 4 pulse-COI3 through the element OR 17, to the input of the counter 6 pulses through the elements OR 18 and 20, to the third input of the trigger 13 through the element OR 18 and sets them to the initial state. In the initial state, counters 4, 6, and 7 pulses and triggers 11-15 are in the zero state, and a unit 5 is recorded in the count pulse 5 and the trigger 15 is written. After the initial setup signal has finished

5 The 4 pulse begins to count the number of clock pulses included in the duration of the radiation P. The decoder 8 determines the number of pulses that must fit into the duration of the radiation T1,

0 and then generates a signal that transmits to the input of the trigger 13 and translates it into a single state. This signal also (through the element OR 17) zeroes the counter of 4 pulses and (through the element OR 20) times5 decides the counter of 6 pulses to count the interval pulses received from the generator of 2 pulses. Pulse counter 6 counts the intervals until the received number matches the number

0 by the pulse counter 5, after which the comparison unit 16 generates a comparison signal. After the initial installation in the counter 5 pulses the number 1 is recorded, therefore, in this case, the signal

5 comparisons are generated after the first pulse of the intervals of the pulse generator 2. The comparison signal also enters the input of the trigger 13 and transfers it to the initial (zero) state, as a result of which the counter of 6 pulses is zeroed (through the element

OR 20) and the 4-pulse counter starts working (removed -, zeroing through the element OR 17). By the same comparison signal, the pulse counter 5 increases its state by one. Such a cyclic repetition of the duration of the radiation T1 and the pauses T2 continues until the number recorded in the pulse counter 6 becomes equal to the number (corresponding to the maximum pause) determined by the decoder 9, after which the decoder 9 generates a signal that is fed to the trigger input 14. The end of the duration of the radiation following the largest pause is the end of the interference simulation cycle (Hz). The peculiarity of starting each next cycle (Hz) as compared to the first one is that during the transition from cycle to cycle there should be no discontinuities in the radiation. This is achieved by resetting the pulse counter 4 without interrupting its counting. To do this, the signal that arrives at the synchronization input of trigger 11 through the element OR 21, and if there is a single signal at its input, a start signal for the next cycle is generated. Thanks to the element And 23, the element OR 21 and the trigger 11. The duration of this signal ends on the falling edge of the first clock pulse of the new cycle. This signal through the element OR 18 restores the trigger 13 and the counter 5 pulses to the initial state, and through the elements OR 18, 20 returns the counter to the initial state

6 pulses. In addition, this signal adds one to the pulse counter 7. After the number of simulation cycles Tc reaches the number determined by the decoder 10, the decoder 10 generates a signal that through the OR element 19 enters the input of the trigger 15 installation into the zero (initial) state, translates it into the initial (zero) state and this closes the key 25, preventing the passage of signals from the noise generator 3 to the output of the noise simulator, and also zeroing the counter

7 pulses. Further resumption of the noise simulator operation is possible only after the trigger signal arrives on the second bus 7 control.

The signals from the output of the interference generator 3 are passed by the key 25 to the output of the interference simulator when the trigger 15 is in the operating state, i.e. about the duration of the radiation T1. The radiation state is detected by the zero state of the pulse counter 6. To avoid the failure of this signal at the boundary of the imitation cycles (Hz), a signal arriving at the element OR 22 is added to it.

Claims (1)

The Invention Simulator is a noise simulator comprising a clock pulse generator connected in series with a first pulse counter and the first decoder, the second pulse counter, the third pulse counter connected in series and the second decoder, the first trigger and the first element I, in series, are connected in series so that, in order to improve the accuracy of the imitation of interference, series-connected pulse generator, fourth pulse counter, comparison unit, second trigger, and first 5 OR element, connected in series the third decoder, the third trigger, the second element OR, the second element AND and the key, the second input of which is connected to the interference generator noise, sequentially 0 connected first control bus, the third OR element and the fourth trigger, the first output of which is connected to the second input of the second AND element, sequentially connected to the second control bus, The fifth fifth trigger and the fourth element OR, the fifth element OR, the sixth element OR, the first input of which is connected to the output of the first element AND, the second input of which is connected to the output of the clock generator 0 pulses with the synchronization input of the first pulse counter and with the synchronization input of the fifth trigger, the output of which is connected to the second input of the first OR element, the output of which is connected to the input 5 of the first pulse counter, the output of the first decoder is connected to the second input of the second trigger and to the second input of the sixth OR element, the output of which is connected to the synchronization input of the first trigger, 0 whose input is connected to the output of the third trigger, the second input of which is connected to the control input of the second pulse counter and to the first input of the second trigger, the third input of which is connected to the first 5 input of the fifth element OR, with the output of the fourth element OR, with the third input of the third trigger and with the synchronization input of the second pulse counter, the outputs of which are connected to the second PODOR group 0 of the comparison unit and with the inputs of the third decoder, the second output of the second trigger is connected to the second input of the fifth OR element, the output of which is connected to the second input of the fourth pulse counter and 5 second input of the second element OR. the output of the fifth trigger is connected to the second input of the fourth trigger, the second output of which is connected to the installation input of the third pulse counter, the synchronization input of which is connected to the second input of the fourth OR element, and to the output of the torus is connected to the second input of the third first trigger, the output of the second decoder element OR.