SU970377A1 - Device for checking comparison circuits - Google Patents

Description

 The invention relates to automation and computing and can be used to control devices of discrete automation and computing.

A device for testing binary number comparison circuits, containing triggers, a logic unit, two counters / outputs of which are connected to the inputs of the reference circuit being tested, is known. .

The disadvantage of the device is low productivity, which limits its scope of use by low-speed comparison circuits, which is associated with the redundancy of encoding the input signals of the monitored circuits.

The closest in technical essence to the present invention is a device for controlling comparison circuits containing an element I, the first counter whose input is connected to the clock bus, the second counter, the logic unit whose first input is connected to the output of the controlled comparison circuit, the first and second triggers the outputs of which are connected to the second and third inputs of logic unit 2,

A disadvantage of this device is also low productivity, due to the fact that the device provides for a complete enumeration of all possible combinations of input signals of the comparison circuit. In addition, the use of the principle of adding a unit (according to the transfer signal from one counter) to the code of the second counter in the pauses between the pulses of the main frequency leads to the need to reduce the working frequency of the circuit 2 times compared to the maximum permissible for this device.

The time t required to test the K bit comparison circuit, having 2 M inputs, is

2

t p. .

Claims (2)

where P is the pulse repetition frequency at the input of the counters / forming the parallel codes. The redundancy of combinations of input variables can be eliminated if we consider that when building multi-digit comparison circuits, comparison elements of low-digit codes are used, which is associated with a limited number of external outputs of the elements интегра integrated circuits in the standard 14 or 16 output block). comparison on w bits contains V elements along k bits each. If checking a comparison element requires a complete enumeration of combinations, the number of which is, then to check the entire comparison scheme, it is enough to ensure sequential enumeration of all the input combinations of the codes of each of the elements with fixed (zero or single) values of logical variables at the inputs of the other elements. Comrade The test time of the comparison circuit in this case is determined by the expression:. 2K T The purpose of the invention is to increase the productivity of the device. The goal is achieved by the fact that in the device for control of comparison circuits, containing two counters, two triggers, element I, block ana. output signals, the input of the first counter is connected to the clock input of the device, the outputs of the first and second triggers are connected respectively to the first and second inputs of the output analysis block whose third input is connected to the output of the controlled comparison circuit the output of the output analysis block devices, an ISI element, two code switches, a third counter, a pulse distributor, and a group of information outputs of the first counter connected to a group of information inputs the first- commutator. the code and the input group of the NAND element whose output is connected to the input of the element I, the second input of which is connected to the first input of the first counter, the output of the element AND connected to the input of the second counter, the group of information outputs of which is connected to the group of information inputs of the second the code switch, the transfer output of the first counter is connected to the input of the third counter, the unit of the first trigger and the first zero input of the second trigger; the transfer output of the second counter is connected to the first zero input of the first trigger and a single input of the second trigger, the transfer output of the third counter is connected to the input of the pulse distributor and the second zero inputs of the first and second triggers, the output group of the pulse distributor is connected to groups of control inputs of the first and second switch codes, the outputs of which are connected respectively to the first and second groups of inputs controlled comparison circuit. The drawing shows a block diagram of a device with a controlled comparison circuit. The device contains counters 1 3, a pulse distributor 4, an AND-NE element 5, an AND 6 element, switches 7 and 8 codes, triggers 9 and lOj a controlled comparison circuit 11, an output analysis unit 12, a clock input 13 of the device, an output 14 of the device. Outputs 1 ,. . . , To the first 1 and second 2 counters, connected respectively to the inputs 1, ...,. To the first 7 and second 8 switches, the codes are information outputs of parallel binary codes of the counters. The transfer output of the first counter 1 is connected to the input of the third counter 3, as well as to the installation input 1 (S) of the first trigger 9 and the installation input O (R) of the second trigger 10, the transfer output of the second counter 2 is connected to the inputs of the installation O and 1 of the trigger 9 and 10 respectively, and the output of the third transfer. the counter 3 is connected to the input of the distributor 4 pulses and to the second inputs of the installation O of the flip-flops 9 and 10. The first (second) switch of codes 7 (8) has M outputs connected to the first (second} group of inputs of the controlled comparison circuit, and M outputs are divided into -V groups of K bits in each. The number of the group of outputs on which the output signals of the first (second / counter 1 (2)) are repeated is determined by the number of the excited output of the distributor .4 pulses, the outputs of which are connected to the control inputs 1 ,. .V of both switches 7 and 8 codes. In yes Let us assume that the first group of inputs of the controlled comparison circuit receives the number A, the second group of inputs has 1 NUMBER B. For the sake of certainty, when describing the principle of operation of the device, it is assumed that all counters switch on the falling edge of the positive impulse to the input of the counter, the output signals transfers of counters are produced when the counter transitions, from the 1 ... 1 state to the 0 ... 0 state in the form of pulses that coincide in duration and polarity with the pulses at the counter inputs. Before the start of operation, counters 1 - 3, triggers 9 and 10 and the distributor 4 pulses are set to zero (depot zero setting is not shown, while the output 1 of the distributor 4 pulses is in the state of a logical unit, the rest (2 ... V) outputs - in the state of logical zero. The device works as follows: With the arrival of pulses at the clock input 13 of the device, the counters 1 and 2 simultaneously change their states, maintaining the equality of the codes until the appearance of the combinations 1., 1 Triggers 9 and 10 are in this case null. states, which corresponds to the equality of the Ive numbers in counters 1 and 2, respectively. With the presence of code 11 ... 1 in the first counter 1, a zero level signal is generated at the output of the IS-NOT element 5, which prevents the passage of the next pulse from the clock the input 13 of the device over the element Ib to the input of the second counter 2, therefore in the next cycle the first counter 1 is set to the zero state, forming a signal at the output of the transfer, and the second counter 2 remains in the state 1 ... 1. The code of the number A in the first counter 1 turns out to be less than the code of the number in the second counter 2, which is fixed on the triggers 9 and 10. The signal from the transfer output of the first counter 1 sets the first trigger 9. In state 1 and confirms the zero state of the second trigger 10. With input to the clock input. 13 of the (2 + 1) pulse device, the second counter 2 is set to the zero state, the inequality of the codes in the counters 1 and 2 changes its sign to the reverse one (A B), the signal from the transfer output of the second counter 2 sets the second trigger 10 to one state and to the zero state the first trigger 9. The inequality persists until the second transition of the counter 1 from the state 1 ... 1 to the state 0 ... 0, while the arrival of the next clock pulse to the input of the second counter 2 is inhibited, as and in the first cycle of operation of the counter 1, the element AND-NOT 5. With each cycle of work The first counter of the delay in the appearance of the transfer signal at the output of the second counter 2 relative to the moment of the appearance of the transfer signal and the output of the first counter 1 increases by one cycle, and after 2 cycles of the input frequency, which corresponds to 2 cycles of operation of counter 1, this delay is 2 cycles, i.e. the codes in counters 1 and 2 take the same values 0 ... 0. The number of cycles of the first counter 1 is counted by the third counter 3 having the same number of bits as the counter 1. The transfer signal of the third counter 3 sets the triggers 9 and 10 to zero states at the moment when the codes of the numbers in the counters 1 and 2 take the values 0 ... 0, i.e. condition A 6 is satisfied (after the completion of the formation of a sequence of all possible combinations of codes at the outputs of the account; d1kov 1 and 2). At the same time, the transfer signal of the third counter 3 switches the distributor of 4 pulses to the second state, in which all its outputs, except the second, are set to signals with a logic zero level. In each of the V states of the distributor of 4 pulses, the switches of codes 7 and 8 transmit all possible combinations of codes from the outputs of counters 1 and 2, respectively, to the same groups of inputs of the controlled comparison circuit: in the first state of the distributor of 4 pulses, the first switch of 7 codes connects the outputs of the first, the counter 1 to 1 ... To the inputs of the number A of the comparison circuit, the second switch 8 codes - the outputs of the second counter 2 to 1 ... To the inputs of the number 8, in the second state of the pulse distributor, the counters 1 and 2 are connected to the inputs (K + 1 ) ... 2K numbers A and B controls uemoy comparing circuit it.d. On all remaining inputs of the comparison circuit in all. The t-states of the 4-pulse distributor are supplied with constant logical signal levels (zero or one). Thus, all possible combinations of input codes in each group of To inputs of the controlled comparison circuit are sequentially iterated with the same input signals on all remaining (V - 1) To inputs for numbers A and 8 "The comparison circuit verification cycle ends with the completion of all combinations codes on the last group of inputs from (M-K + l to M of the controlled comparison circuit, the output signals of which, coming to the input of the output signal analysis unit 12, are compared in it with the states of the flip-flops 9 and 10. For a healthy Comparisons in each cycle of operation of the device the following conditions must be met for the output signals of the comparison circuit with the output signals of the flip-flops 9 and 10: If these conditions are not met, the output analysis unit 12 transmits an alarm signal to the device output 14, which can be used to locate malfunctions in the controlled comparison circuit by prohibiting the supply of signals to the clock input 13 of the device and subsequent analysis of the odes stored in counters 1 and 2. (The proposed device in comparison with devices similar in purpose, but using the principle of complete enumeration of all input .. combinations of codes, allows to increase productivity by the number of N times determined by the ratio of time t and T The gain in speed is obtained the greater, the greater the magnitude of the controlled comparison circuits since the power dependence of the duration of the control interval on the number of bits is replaced by the linear dependence of the specified parameter on the number of groups into which the bits are divided. . The invention The device for controlling the circuits containing two counters, two triggers, element I, a block analysis of output signals, the parvbgo counter input connected to a clock input of the device, the outputs of the first and second triggers are connected respectively to the first and second inputs of the output analyzer signals, the third input of which is connected to the output of the controlled comparison circuit, the output of the output signal analysis unit is the output of the device, which is the one with which / what, in order to improve performance, an IS-NOT element is entered into it, Two code switches, a third counter, a pulse distributor, and a group of information outputs of the first counter is connected to a group of information inputs of the first code switch and a group of inputs of the AND-NE element whose output is connected to the input of the AND element, the second input which is connected to the first input of the first counter, the output of the element I is connected to the input of the second counter, the group of information outputs of which is connected to the group of information inputs of the second switch of codes, the output of the transfer of the first The first counter is connected to the input of the third counter, the single input of the first trigger and the first zero input of the second trigger, f the transfer output of the second counter is connected with the first zero input of the first trigger and the single input of the second trigger, the transfer output of the third counter is connected to the input of the pulse distributor and the second zero inputs of the first and second triggers, the group of outputs of the pulse distributor is connected to the groups of control inputs of the first and second switches of the codes, the outputs of which are connected according to enno the first and second groups of inputs controlled by the comparison circuit. Sources of information taken into account in the examination 11 USSR Author's Certificate No. 481898, cl. G About F 11/00, 1973. 2. USSR author's certificate 584309, cl. G About F 11/00, 1976 (prototype).