SU563713A1 - Analog-to-digital converter - Google Patents

Description

one

The invention relates to computing technology and can be used in the technology of analog-digital converters (ADC).

A known analogue converter is a code containing ADC, clock registers, a clock generator, a decoder, and a control device 1. However, it has a low speed.

A analog-to-digital converter is known, which contains a three-phase clock generator and pulse clock, a clock register, a comparison device, a result register, a decoder, a result correction block and a decoding converter, the output of the latter is connected to the first input of the comparison circuit, the output of which is connected to the second input. the converted voltage, and its output is connected to the first input of the result register and to the first input of the decoder, the output of which is connected to the first input of the result correction block, the output of the last It is single with the second input of the result register and the second input of the register of cycles, the output of which is connected to the second input of the decoder, the third, input of which is connected to the output of the result register and the input of the decoding converter; the first, second and third outputs of the clock generator are connected respectively to the third input of the circuit comparison, to the second input of the result correction unit 2. When the impulse noise value appears in the measurement circuits of the coded value, the final result of the conversion may differ significantly ie the true result.

The aim of the invention is to increase the noise immunity of the analog-to-digital converter with respect to the impulse noise arising in the coding measurement circuit

quantities.

This is achieved in that an analog-to-digital converter containing a control device connected to the result correction unit, the result register,

The clock generator and clock register, the output of which is connected to one of the decoder inputs, to the other input of which the output of the result register is connected, the output of the decoder is connected through a result correction unit with correction and inputs of the register of measures and result register, the output of the result register through a decoding converter is connected to the first input of the comparison element, to the second input of which the output of the source of the transformed iair is connected, and with the third century of the comparison element the first output is connected od clock generator, the number of pulses counter administered survey comparing element,

the counter of the number of actuations of the element Comparative, the block of logic elements, valves, triggers, the output of the element is connected to the single input of the first trigger, the output of the nerve trigger is connected to the input of the first valve, to the other input of which the first output of the clock generator is connected, the outputs are connected, and the outputs of the first valve are connected. . h.doc. to the counting input of the counter of the number of pulses of the interrogation of the comparison element, the output of which is connected to the uiravl 101CIM input of the second valve, through the second input of which the second output of the generator The operating pulses are connected to the setup input of the counter of the number of polling pulses of the reference element, to the "zero input of the first trnger and to the installation input of the counter of the comparison element triggers, to the counting input of which the output of the comparison element is connected, the first output of the counter of the number of operations e; It is connected with uiravl yugzim by the input of the third wave, through the second input of which the third output of the clock emulators is connected to the clock input of the clock register, and to ch1) avl yupmem register input 1Uchep output of the second trnger, "the typical input of which is connected to the second output of the counter of the number of operation of the comparison element," the zero input of the second trigger is connected to the first output of the clock generator; interrogation of the comparison element, the counter of the number of operations of the comparison element and the nerve trigger, the second input of the block of logic elements is connected to the output of the register of cycles, and the output of the x sootvetstvuyup1 elements connected to he entry of result register.

The drawing shows a structural diagram of the proposed analog-to-digital converter.

The converter contains the element 1 of the comparison, the counter 2 of the number of the element of the trigger, the trigger 3, the trigger 4, the geyrator of 5 clock emulses, the counter 6 nm pulses f) of the match element, the speed index 7, the register of 9 cycles, the trigger 10, block 11 of the charts, the elec- The converter 12, the reg result 13, the decoding converter 14, the source 15 of the measured voltage, the result correction block 16, the control device 17.

The output of the comparison element 1 to the counter input of the counter 2 and the one input of the trigger 3, the output of which is connected to the control input of the valve 4, through another input of which the first output of the 5 clock pulse generator is connected to the counting input of the counter 6. The counter 6 controls valve 7, through which the second output of the heater 5 connects to the set inputs of counters 2 and fi and the trigger 3. The first output of counter 2 controls the septile 8, through which the third output of the generator o is connected to the clock input of the register 9 clocks, the second output tchika 2 soedppen with ustapovochpym input flip-flop 10, whose output is connected to the control inputs of the logic unit 11 and register elements 9 cycles. The latter is constructed in such a way that the absence of the sigpal on the control input through the clock input is carried out by the unit recorded in the first cycle, and the signal input signal is advanced in the register through the bit. The register output 9 cycles is connected to the input of the decoder 12 and through the block 11 logic elements with the input of the result register 13, the output of which is connected to the second input of the deifferator 12 and through the decoder converter 14 to the input of the element 1, with the second input of which is connected the output of the source 15 Fuck

To the third input of the element 1 there is a second output of the heater 5, which is also connected to the installation input of the trigger 10. The output of the decoder 12 and the key switch through the result correction block 16 to the correcting input register 13 of the result register and the 9 clock register. The setting 17 of the device is assigned to the initial state of the registers 13, 9, the counters 2, 6 of the trigger 3, for which the output of the ycTpoiicTBa 17 is connected to the installation inputs of the pointer elements. The second output of the device 17 is connected to the control input of the result correction unit 16, and the third output to the input of the heater 5.

Consider the operation of the ADC for the case when the interval of the determination is equal to (O-8). In order to ensure the optimal coding of information in the conditions of the action of single-point impulsive interferences (i.e., for the minimum number of cycles), the following discharge weights should be selected, starting with the highest, 3,2,1,1.

The operation of the converter consists of three modes:

--- a mode where there are no failures in the process of digital conversion both in the memory modules under the influence of interference and in the comparison element under the influence of external objects;

- there is no register of elements of this type of register and a register of the result, however, a single negative negative interference interfered with the circuit of the code-controlled variable;

--- There are failures of the memory of registers of clocks and result.

Suppose that the LCP operates under the conditions of impulse noise of negative polarity, and the comparison element operates according to the following condition: the signal from the output of the element is compared to Q;, c is equal to

Qge 1 if

(1) (2) Q, e 0, if and / - and ,,.

The converter works as follows.

The control device 17 generates two commands at the beginning of the coding: the first sets the initial 3 zero states trigger 3, counters 2 and 6, registers 13 and 9, and the second starts the generator 5, each clock cycle includes three micro cycles. On the first micro-tact, through the gate 8, the unit is promoted in the corresponding (/ C-D1) -th or (/ (- | -2) -th register bit 9, which through block 11 of the logic elements sets the "single state ()" th or (/ (- r2) th trigger in the result register 13, which controls the corresponding bit of the decoding converter 14, which corresponds to the addition of (X + 1) th or (/ (4-2) -th reference) to the previously existing reference In the second microtack, the element 1 is compared, the information is recorded in the counter 2 and 6 and the "Null state flip-flop 10, and the third mikrotakte mounted B null state trigger 3 and the counters 2 and 6.

Nust the transformed voltage U is equal to 2.5 arbitrary units. Then, after starting the generator, in the first micro tact of the first clock cycle, the first standard of the decoding converter will be connected to the second input of the element 1 (in the case of equal weight to three conventional units). On the second microtack, the output of element I will be a "single signal, since the condition

(1) and the trigger 3 is set to "one state, and counters 6 and 2 will be recorded one at a time. In the third micro tact, trigger 3 and counters 2 and 6 retain the information recorded in them, since counter B prohibits clock emulsions from passing through valve 7. Since element 1 has triggered in the first cycle, element 1 will be polled in the second cycle

the relationship between U and U, as in the previous clock cycle. Therefore, in the first micro tact of the second clock pulse of the generator 5 does not pass through the ventilation 8, the control input of which contains the inhibiting potential of counter 2. In regstar 9 and 13 there is a combination of 1000. In the second microtak the element 1 will trigger according to condition (2). In counters 2 and 6, the unit will be added one by one, and the number "10 will be set in them, and the trigger 10 will change to" one state. On the third micro tact of the second clock cycle, the information from the counters 6 and 2 will be erased and the trigger 3 will be set to the “zero” state, since the control potential of the valve 7 will be at the control input. The first cycle of the third clock cycle in registers 9 and 13 will record the number 0010, i.e. the connection will be made not of the next () standard, but () the standard, which is provided by trgger 10, which prepares the corresponding circuits for the control input of the register 9. The further work of the ATSN and the already considered two conversion cycles are presented in Table 1.

T a b l II c a 1

The result of encoding the OOP is generated in the result register 13.

The operation of the converter in the second mode will be considered for the cases when, in 5 conventional units and on the second cycle, there is a single disturbance with an amplitude much greater than the magnitude of the reference voltage. The operation of the ACS in which mode is described in Table. 2

From the considered examples it can be seen that counters 6 and 2 together with triggers 10 and 3, valves 4, 7 and 8 should ensure in the case of double triggering of element 1 at the next tact of the nrod:; unit reduction in register 9 through the discharge and oryros of element 1 Thus, in the least number of clocks, this instructor allows, during the formation of the output code, to detect and correct the result of the effect on the second cycle of a single negative interference.

In the third mode, a sign of failure is the coincidence of the states of the same trigger in registers 9 and 13, which is detected by the decoder and, by a command of the control unit 17, the result correction unit 15 is corrected.

Formula and 3 about b and e and

An analog-to-digital converter containing a control unit connected to a result correction unit, a result register, a clock pulse generator and a register of clock cycles, the output of which is connected to one of the inputs of the depumer, to another input of which the output register code is connected, the output of the decoder is connected through the result correction block with the correction inputs of clock registers and the result register, the output of the result register through a decoding converter is connected to the first input of the element compared to The output of the source of the voltage being converted is connected to the second input, and the first output of the clock generator is connected with the third input of the reference element, which is based on the fact that, in order to reduce the noise immunity, the counter of the number of pulses of the reference element is entered into it, count of the number of operations of the element} 1ta

block of logic elements, valves, triggers, the output of the comparison element is connected to the single input of the first trigger, the output of the first connection trigger with the gain input of the first valve}: to the other input of which the first output of the clock generator is connected, the output of the first valve is connected to the counting the input of the counter of the number of pulses of the interrogation element of the comparison, the output of which is connected to the control input of the second valve, through the second input of which the second output of the clock pulse generator is connected to the installation the input of the counter of the number of pulses of the interrogation of the comparison element, the zero input of the first trigger and the installation input of the counter of the number of operation of the comparison element, to the counting input of which the output of the comparison element is connected, the first output of the counter of the number of operation of the comparison element is connected to the second input of which the third output of the clock pulse generator is connected to the clock input of the clock register, and to the control input

the input of the register of clock cycles and the worm. to the input of the block of logic elements are connected to the output of the second trigger, the "single input of which is connected to the second output of the counter of the number of operation of the comparison element," zero input

The second trigger is connected to the first output of the clock generator, the output of the control device is connected to the installation inputs of the counters of the number of polling pulses of the comparison element, the counter of the number of operations of the comparison element and the first trigger, the second input of the logic elements block is connected to the output of the clock register, and the output of the logic elements block It is connected to the appropriate .mu input register of the result.

Sources of information taken into account

9 1. USSR Author's Certificate No. 444985, cl. G 01R 13/02, 30.06.72.

10 2. USSR author's certificate No. 310270, cl. H OZK 13/02, 23.03.70.