SU834927A1 - Counter testing de - Google Patents

Description

one

The invention relates to a pulse and instrumentation technique and can be used in time interval meters, current time sensors, operation counters, etc.

A device for controlling a counter is known, which contains a control trigger, a decoder, a logic and coding block, and a fault indicator l.

. The disadvantage of this device is limited functionality.

It is also known to control a counter device comprising a driver for control pulses / a display unit, a comparison unit and a memory unit, with the output of the display unit connected to the input; the control pulse generator, the first and second outputs of which are connected to the inputs of the counter and the comparison unit, respectively; the first group of inputs of which is connected to the outputs of the counter

21 Not a well-known device is the complexity of the hardware implementation, which is associated with the need to generate reference signals.

The purpose of the invention is to reduce hardware costs.

The goal is achieved by the fact that in the meter control device containing a driver of control pulses, an indication unit, a comparison unit and a memory unit, the output of the display unit is connected to the input of the control pulse generator,

0 the first and second outputs of which are connected to the inputs of the counter and b., Respectively. Comparison, the first group of inputs of which is connected to the outputs of the counter, the outputs of the counter are connected to the inputs of the memory unit, the clock input of which is connected to the third control driver driver, and the outputs of the memory block are connected to the inputs of the block as compared to.

The block diagram of the meter control device is shown in the drawing.

The control device of the counter 1 contains the driver control 2

5 pulses, an indication unit 3, a comparison unit 4 and a memory unit 5, the output of the indication unit 3 connected to the input of the driver 2 control pulses, the first and second outputs

0 which is connected to the inputs respectively of the counter 1 and the comparator unit 4, the first group of inputs of which is connected to the outputs of the counter 1 connected to the inputs of the memory unit 5, the clock input of which is connected to the third output of the driver 2, the control pulses These are connected to the inputs of unit 4 of the comparison.

 The device works as follows.

in a way.

At the beginning of operation, the counter 1 is in the zero state, the state of the memory block 5 is indifferent. By the first clock pulse coming from the output of the former 2 to the clock input of memory block 5, the latter remembers the current or subsequent state of the checked counter 1. With the arrival of the clock pulse through the counting input of the counter 1, the latter changes its state by one . The clock pulse received at the input of the comparison unit 4 compares the numbers coming from the memory block 5 and the counter 1. The correct operation of the counter is characterized by the equality of these numbers (if the next state of the counter 1 is recorded in memory block 5), or the difference in unit (if the current state of counter 1 is recorded in memory block 5).

After this operation, the cycle of operation of the device is repeated.

In the event of a malfunctioning operation of the counter. 1, the above conditions are violated and the comparison unit 4 generates an error signal to the display unit 3, which prohibits the insertion of a false code combination from the counter 1 and stops the operation of the driver 2.

Claims (2)

1. USSR author's certificate number 281903, cl. G06 F 11/10, 1967. 2. Shl pobersky v.I. Fundamentals of technology for the transmission of discrete messages, M., Svz, 1973, p.475, fig.10.5 (prototype). "" "| / g: