SU1211876A1 - Controlled frequency divider - Google Patents

Abstract

The invention relates to pulse engineering and can be used in measuring and computing devices. The purpose of the invention is to increase speed. The device contains a pulse counter 1 consisting of n serially connected flip-flops 2-1, 2-2, ..., 2-n, input 4 and output 3 tires, elements 5-1, 5-2, ..., 5 - compare, control bus 6, elements AND 7 and 8, element OR 9 and trigger 10. In the description, the electrical circuit of the reference element included in the controlled frequency divider is given, and three possible cases of the result of the comparison are considered. 1 3 .p .. f-ly. 2 Il. C & (ABOUT

Description

one

The invention relates to a pulse technique and can be used in measurement technology and in computing devices.

The purpose of the invention is to increase speed.

FIG. 1 shows an elegant: trichesky structured circuit of a controlled frequency divider; Fig. 2 is an electrical circuit of a reference element included in a controlled frequency divider.

The controlled frequency divider contains a counter of 1 pulses, consisting of C series-connected triggers 2-1, 2-2, ", .5 2-Г |. The reset input of the counter 1 pulses is connected) with the output bus 3, the counting input with the input bus A, the outputs of the counter of 1 counter pulses (each of the h triggers 2-1, 2-2,. 2.) Are connected to the first inputs of the corresponding elements 5-1.5-2 ... 5-c compared to the second inputs of which are connected to the corresponding bits of the control bus 6, the third input of each of the elements of the comparison, except the last 5-c, is connected to the first output the subsequent element of the comparison, the first and second elements 7 and 8 AND element 9 SHS and trigger 10, the output of which is connected to the output bus 3, in the starting stroke is with the output of the first element 7 I, the first input of which is connected to the input bus 4 and with the direct input of the second element 8 I, the output of which is connected to the reset input of the trigger 10, inverse and the second input of the first element 7 I and c the output of element 9 OR whose inverse input is connected to the first output of the first comparison element 5-1, and each of the li-direct inputs to the second output of the corresponding element 5-1.5-2. ,, 5-VI comparison.

Each of the comparison elements of the controlled frequency divider contains three elements 11-13 AND and the JIFIH element 14, wherein the first input 15 of the comparison element is connected to the direct input of the first element 11 AND, and to the inverse of the second element 12 AND, the second input 16 the comparison element is connected to the inverse input of the first element 11 I and to the direct input of the second element 12I, the output of the first element I 11 is connected to the direct input tert-: .-;

That 13 And, the output of the second element And 12 is connected to the first pass of Elimat 14 OR, the third input 17 of the equator element is connected to the inverse input

the third element 13 And to the second input element 14 OR, and the outputs of the element 14 OR and the third element 13 And connected respectively to the first and second outputs 18 and 19

element of comparison.

The controlled frequency divider operates as follows.

When pushing the bus 4 sequences w 1puls counter 1

changes its state until the triggers 2-1, 2-2, .. 2-P are set to the state corresponding to the code on the bus 6. Until then, at the outputs of element 9 and the-trigger 10

the zero level is set, and the pulses from the bus 4 through the element 8 come to the reset input of the trigger 10, which confirms its zero state.

3 The moment of coincidence of the state of the flip-flops 2-1.2-2 ... 2-c of the counter 1 with the code on the corresponding bits of the bus 6 at the second outputs of the elements 5--1, 5-2. . .5- P set low potential. At the same time, the low potential supplied to the IPI 9 inverse input from the first output of element 5-1 provides a high potential from the output of an element SH-9 to the second input of element AND 7 Another impulse from bus 4 passes through element AND 7 to the trigger trigger input 10 and translates it into a single state. This ensures the appearance on the high potential bus 3, which transfers the triggers 2-152-2 ... 2 - n of the counter 1 to the zero state. At the same time, a high potential is established on the first output of element 5-1, and on the second outputs ECtx

elements 5-1,5-2 ... 5- And - low. This ensures the installation of a low potential supplied to the inverted input of an element 8 at the output of the SHS 9 element. Another pulse from the bus 4 via the AND 8 element enters the reset input, three of 10, transfer. Egs to zero state. With a low potential at the output of the trigger 10, the formation of the output pulse on bus 3 is completed and the reset signal is removed from the reset inputs of the triggers 2-1.2-2 ... 2-M counter 1, At the end of the same

the input pulse trigger 2-1 of the counter 1 is set to one and further operation of the counter 1 is carried out in the usual way,

The operation of the comparison element is to compare the code on bus 6 with the code corresponding to the state of the triggers of counter 1 and generate a control signal at the input of the element OR 9 in the case of equality of the compared codes (low potential at the inverse input of the element OR 9) or if the code on bus 6 is less (high potential at any direct input of the element OR 9),

Consider three possible cases of the result of the comparison.

If the codes specified are equal, then the same signal is applied to the inputs 15 and 16 of each reference element. At the outputs of the elements And 11 and 12 low potential. Consequently, at outputs 18 and 19 of all elements 5-1.5-2 ... 5 -p, the potential is low, and from output 18 of element 5-1, a low potential is fed to the inverse input of element 9.

Now suppose that the codes being compared do not match. The result of the comparison is determined by the highest of the non-coincident bits of the compared codes. Let the highest of the non-coincident bits be –YY (1 with I: fi)

bit d

If the inputs 15 and 16 of the element 5- i (not shown in Fig. 2) are low and high potentials, respectively, then the code on the control bus 6 is greater than the code written in counter 1. In this case, the output of the element 12 and output 18 of element 5-i high potential, providing elements 5-1.5-2 ... 5 to inputs 17 and outputs 1B high potential, l on outputs 19 is low Consequently, inverse input 9 is high potential , and at the other entrances - low.

If high and low potentials are respectively input to inputs 15 and 16 of element 5-I, then the code on bus 6 is less than the code recorded in counter 1. In this case, the output of element 11 and the output 19 of element 5-i have a high potential. Consequently, at the input of element 8, connected to the output 19 of element 5-i is a high potential.

The process of tuning the frequency divider to the new division factor

is speedless, and the time of the next output pulse since the code change on bus 6 depends only on the current state of counter 1. Suppose that h 1 pulses are recorded in counter 1, and according to the new code on the bus 6, every N -and input pulse. Then when N p, the next output pulse will be

N -and, and at М S (, at the output, according to Wits, (n ± 1) -th input pulse and then every Nth.

Claims (2)

1. A controlled frequency divider containing a pulse counter, consisting of n in series with single triggers, the reset input of which is connected to the output bus, the counting input with the input bus, the discharge outputs of the pulse counter are connected to the first inputs of the corresponding comparison elements, the second inputs of which are connected with the corresponding; The bits of the control bus, the third input of each of the comparison elements, except the last one, is connected to the first output of the subsequent comparison element, and the first and second AND elements, characterized in that, in order to increase the speed, an OR element and a trigger, the output of which is connected to the output bus, are introduced into the start input - with the output of the first element AND, the first input of which is connected to the input bus and with the direct input of the second element AND, the output of which is connected with the trigger reset input, the inverse input — with the second input of the first element AND, and with the output of the OR element, the inverse input of which is connected to the first output of the first comparison element, and each of the right forward inputs — with the second output of the corresponding comparison element. 2. The divider according to claim 1, about tl and - due to the fact that the comparison element contains three elements AND and an IC element, and the first input of the comparison element is connected to the direct input of the first element And to the inverted input of the second element And, the second input of the comparison element is connected to the inverted input of the first element And to the direct input of the second element And, the output of the first element And is connected to the direct input of the third element And, the output of the second element And is connected to the first input the element OR, the third entry the comparison element is connected to the inverse input of the third element Nick to the second input of the OR element, and the outputs of the OR element and the third AND element are connected respectively to the first and second outputs of the comparison element. nineteen FIG. 2