SU1261108A1 - Pulse repetition frequency divider with variable countdown - Google Patents

Description

11Z61108

The invention relates to a pulse: technology, is an improvement of the pulse frequency divider according to auth.St. USSR № 1102043 and

meter 5 is used in devices; trigger 11; register 13 is set to

equipment, automation and telemechanic.

The purpose of the invention is to increase the reliability of the device when changing

zero state. On tires 6, a code is set corresponding to the selected division factor. At the exit of element 4 there is a level

the dividing ratio code is due to the us-y unit, and at the output of the element 5 of the tran- sition possibility of changing the division code to the end of the division cycle.

The drawing shows a structural diagram of the proposed controllable follow-up frequency divider.

The device contains a counter 1 pulses on the trigger, the first trigger 2, the elements 3 match, the first 4 and second 5 elements OR, bus 6 control division factor code, input bus 7, output bus 8, the first 9 and second 10 elements 2I-NOT, second trigger 11, inverter 12 and register 13.

In this case, the counting input of counter 1 is connected to the input bus 7, and its zero outputs are connected to the first inputs of the corresponding elements 3 matches, the outputs of which are connected to the corresponding inputs of the first element 4 OR, the output of which is connected to the single input of the first trigger 2. The first input of the second element OR 5 is connected to the input bus 7, the remaining inputs are connected to the single outputs of the corresponding trigger counters of 1 pulses, the output is with the zero input of the first trigger 2. The first 9 and second 10 elements 2I-NOT with their first inputs They are sent to the input bus 7, and the second to the single outputs of the first 2 and second 11, respectively, triggers. The zero input of the second trigger is connected respectively to the zero input and the single output of trigger 2, the output of the second element Yu of the 2I-NOT connected to the OUTPUT1 bus 8 of the device and connected to the zero inputs of the trigger of the pulse counter 1, and the output of the first 9 element 2I-NOT connected to C - input of the second trigger 11. The information inputs of the register 13 are connected to the bus 6 of the control of the dividing coefficient code, the outputs to the second inputs of the corresponding elements of the 3 matches, and the C input through the inverter 12 is connected to the output of the second 5 of the OR element.

The device works as follows.

In the initial state, all the triggers of the counter 1, trigger 2, additional

zero state. On tires 6, a code is set corresponding to the selected division factor. At the output of element 4 there is a level

level zero. The division factor is determined by the expression Cd K + 1, where K is the binary code of the division factor, fed to the control bus 6.

When the input signal arrives, the counter 1 counts the input pulses, while the logical element M appears at the output of the element OR 5 (the logical level O at the output of the inverter 12). Pulse counting continues until it is | | and overflow of counter 1 and at its zero outputs, as well as at the output of the element OR 5, establish zero levels and, accordingly, a single level at the output of the inverter 12. The transition from O to 1 at the output of the inverter 12, affecting the C input of the register 13, records of the dividing rate code, to the output of register 13, after which counter 1 resumes counting the input pulses until a code is set in it that matches the binary code at the output of the register 13. Before this, at least one of the 3 matches matches the output unit level. When the code 1 in the counter is set to coincide with the binary code of the division factor, zero levels appear at the outputs of all elements 3, and therefore a level zero appears at the output of element 4 OR, which sets the unit level at output of trigger 2 acting on the D-input of the second trigger 11 and the second input of the first element 9 2I-NOT, resulting in a zero level at the output of the latter. Therefore, at the moment when the input pulse ends at the input bus, at the unit output of the second trigger 11 at the input D

a single level signal acting on the second input of the second element 10 2I-NOT. With the coming of the next

31

the input pulse at the input of the element 10, and thus on the output bus 8 of the divider, a zero level signal appears and starts. setting the triggers of the counter 1 to the zero state. The value of the signal at the output of element 5 is determined by the state of the triggers of counter 1 and the value of the output signal of the divider. At the same time, on the output bus 8 of the divider, the output pulse of the divider ends, and at the output of element 5, a level of zero appears (at the output of the inverter 12, the level of one), and the triggers 2 and 11 are set to the zero state. At the same time, the difference of zero - a unit at the output of the inverter 12, affecting the C input of the register 13, writes (or confirms) the division code from the control buses 6 to the output of the register 13. Subsequently, the divider works in a similar way. As a result, pulses with a frequency proportional to the frequency of the input pulses and the S. Lisin pattern are generated on the output bus 8 of the divider. Order 5244/57

Compiled by S. Klevtsov Tehred L. Oleinik

Corre

Circulation 816 VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

2611084

It is proportional to binary code

on the bus 6 plus the unit.

The use of an inverter and a register to record the current value of the k-d division factor makes it possible to eliminate possible malfunctions in the operation of the device, which increases the reliability of its operation as a whole.

Claims (1)

Invention Formula Controlled impulse frequency divider by avt., Sv.1102043j 15 about tl and ch and y with the fact that, in order to increase the reliability of work when changing the code of the division factor, an inverter and a register are entered into it, the information inputs of which are 20 are connected to the control buses of the dividing coefficient code, the outputs to the second inputs of the corresponding coincidence elements, and the C input through the inverter is connected to the output of the second OR element. Proofreader M.Maksiminshynets Subscription