SU1596266A1 - Apparatus for measuring the ratio of pulse sequence frequencies - Google Patents

Abstract

The invention relates to a pulse technique and can be used to improve the accuracy of measuring the ratio of the frequencies of pulse sequences. The purpose of the invention is achieved by introducing into the device an adder 8, a sensor 9 of a single code and new functional connections. In addition, the device includes a reversible counter 3, a differential frequency driver 4, a controlled frequency divider 5, and a blocking element 6. Inverts the low-order code of the reversible counter 3 supplied to the control inputs of the controlled frequency divider 5, and incrementing by one in the adder 8 the direct output code of the reversing counter 3 leads to the formation of hysteresis cycles depending on the output device code on the input frequency ratio, which by eliminating the uncertainty in the representation of the output, the measurement accuracy is improved. 2 Il.

Description

The invention relates to a pulse technique and can be used to measure the frequency of the pulse signals.

The aim of the invention is to improve the measurement accuracy by eliminating the uncertainty in the representation of the measurement result.

Fig. 1 is a functional diagram of a device for measuring the frequency ratio; Fig 2 is a functional diagram of the blocking element.

The device contains the first input bus 1, the second input bus 2, the reversible counter 3, the differential frequency generator 4, the control divider 5 frequency, blocking element 6, the output bus 7, the adder 8 and the unit code sensor 9.

The first and second input buses 1 and 2 are connected respectively to the input of the controlled frequency divider 5 and to the subtractive input of the differential frequency generator 4, the first and second outputs of which are connected to the first and second inputs of the blocking element 6, the output of which is connected to the reversing counting input the counter 3, the input of the counting direction of which is connected to the second output of the differential frequency generator 4, the summing input of which is connected to the output of the controlled frequency divider 5. Output 15 bus 7 is connected to the output group of all the bits of the adder 8, except for the younger one. The outputs of the sensor 9 of the unit code are connected to the inputs of the first term of the adder 8, the inputs of the second term of which are connected to the outputs of the reversible counter 3, the group of discharge outputs of which, except for the low power bit, is connected to the information inputs of the blocking element 6 and the group of control inputs of the control frequency divider 5, the control input of which is connected to the inverse output of the lower order of the reversible counter 3, the blocking element 6 contains the element OR 10, the element AND NOT P, the switch 12 and the element AND NOT 13, The input inputs of blocking element 6 are connected to the inputs of element OR 10 and element I-HE 11, the outputs of which are connected respectively to the first and second inputs of switch 12, the output of which is connected to the first input of element 13 and whose output is the output of blocking element 6, and the second the inputs of the blocking element 6 are connected respectively to the control input of the switch 12 and to the second input of the element NAND 13. The device operates as follows. The sequences of the pulses of the dividend and the divider with frequencies f and f, respectively, come from the first and second input buses 1 and 2 ka of the input of the controlled frequency divider 5 and the melting input of the difference frequency generator 4. At the output of the controlled frequency divider 5, a sequence is formed with a frequency

f,

(1 TO

arriving at the summing input of the driver 4 of the difference frequency, where K is the division ratio of the controllable divider 5 frequencies, set by the Numeric code K on its information inputs, received from the information outputs of the reversible counter 3, the minimum division factor corresponds to the numeric code to the JO; 0; 0;,., 0} O5 on the information inputs of the controlled divider frequency 5, t, e, K K + 1.

satisfying

f, 6

corresponding to the steady state mode of the device.

Provided

one. . f

-, KI

The right part of the expression (2) is different from zero, so the numeric code to on the direct information outputs of the reversible counter 3 oscillates within the measuring interval of 6 From the first output of the differential frequency generator 4, the first input of the blocking element 6 receives a sequence of pulses with a frequency. and the voltage level at the second frequency differential frequency driver 4 input to the counting direction of the reversible counter 3 determines the sign of the frequency difference in formula (2), the logical level 1 corresponding to the inequality ff 2 ° The differential frequency pulses come from the first output of the driver 4 the difference frequency through the blocking element 6 to the counting input of the reversible counter 3 and change its state until the forward information outputs of the reversible counter 3 show one of two numerical values th code, corresponding to the boundaries of the measuring interval, equal to where n is an integer. The values of the numerical codes K and K on the direct information outputs of the reversible counter 3 will correspond, taking into account the inverse information output of the first bit, the division factors K, and K of the controlled frequency divider 5: K, 2, -1; To the limits of one bit and alternately takes the values t, a. subject to the condition f iJ 2 - K, the difference frequency f О and the numerical code K takes one of the values or K2, respectively. From condition (5) it follows that the value of the measured ratio of average values of frequencies is in the interval -fi U ;; K ,, corresponding to the interval K, K I of the numerical code K on the direct information numerical code K on the direct information outputs of the reversible counter 3, When the measured ratio of the average values of the frequencies f and the limits of the measuring interval (8) exit, for example, due to a change in the average value of one of the frequencies f or f, the state of the reversible counter 3 changes and a new one is formed. the measuring interval, which determines the boundaries of the measured ratio of the average values of the frequencies f, and f, for example, with an increase in the ratio of the frequencies when –r – K. generates -g with an interval of 3 k;), and Kz. The process occurs until the device switches to the new steady state corresponding to the new value of the ratio of average values of frequencies f. From a comparison of expressions (4) and (10) it follows that the measure 1e and the intervals formed by the numerical code K partially overlap each other. Thus formed hysteresis cycles, depending on (- |), exclude oscillatory 1 transitions from one measuring and terval to the next in the setpoint mode of operation for any ratio The bottom frequencies fi and f. At the same time, the numerical code K from the direct information outputs of the reversible counter 3 is fed to the information inputs of the adder 8, where the code of the number 1 is added to it, i.e. The numeric code K at the information outputs of the adder is defined as: K K + 1 The addition operation modifies the numeric code to such that each described measurement interval is the ratio of average values of frequencies f and f frequencies f, and f enclosed between states numeric code k. different values correspond to two states of the numerical code K at the information outputs of the adder 8, the higher bits of which, starting with the second bit, remain unchanged within any separately taken measurement interval. This allows you to get at the information outputs of the higher bits, starting with the second bit, the summation P 8, the numerical code K p avny 2 and each of the described measurement intervals corresponds to only one value of the numerical code K or taking into account (4), (8), ( II), (12) -7-2K When the value of the numerical code K exceeds the limit values, the operation of controlled frequency divider 5 having N bits will be violated. Therefore, in order to limit the change of the numerical code K within the specified limits, the information outputs of the higher bits starting from second sp RS-down counter 3 are connected to the data inputs of the locking member 6, which blocks the down counter 3 when the numeric code to the specified limits. The blocking of the reversible counter 3 is as follows, To the second input of the reversible counter 3 and to the second input of the element 6

the locking from the second output of the differential frequency 4 transformer receives a voltage level corresponding to, for example, the subtractive mode of the reversible counter 3, the first input of which from the output of the blocking element 6 receives the differential frequency pulses. The state of the reversible counter 3 changes in the direction of decreasing until all its information outputs of the higher bits, starting from the second bit, do not match the O value, which corresponds to the limit value. At the same time, the arrival of differential frequency pulses from the output of the blocking element 6 to the first input of the reversible counter 3 stops until the voltage level coming from the second output of the differential frequency driver 4 corresponding to the summing up operation of the reverse counter is set at the second input of the blocking element 6 3,

Similarly, the reversible counter 3 is blocked at occurrence of 1 for all its information output of the high-order bits, starting from the second digit, which corresponds to the limit value

Claims (1)

In the proposed device, compared with the prototype device, the uncertainty of the representation of the measurement result at a fractional ratio of the frequencies f and f is injured, which leads to an increase in the measurement accuracy of A device for measuring the frequency ratio of a pulse sequence containing the first and second input buses, a blocking element, a controlled frequency divider, an output bus and a reversible counter, the group of bit outputs of which is connected to the group of control inputs of a controlled frequency divider, the input of which is connected to the first input bus, differential frequency driver, the summing and subtracting inputs of which are connected to the output of the controlled frequency divider and to the second input bus, respectively, that, in order to improve the measurement accuracy by eliminating the uncertainty in the representation of the measurement result, the adder and the sensor of a single code are entered into it, the outputs of which are connected to the inputs of the first term of the adder, the inputs of the second term of which are connected to the forward output of the lower-order reversible counter and group of bit outputs of the reversible counter, the inverse output of the lower bit of which is connected to the control input of the controlled frequency divider, the first and second outputs of the The difference frequency bodies are connected respectively to the first and second inputs of the blocking element, the output of which is connected to the counting input of the reversible counter, the counting input of which is connected to the second output of the differential frequency generator, the information inputs of which are connected to the group. of the discharge outputs of the reversible counter, the group of discharge outputs of the sum-, device is connected to the output bus of the device. 1