SU1106010A1 - Two-channel analog-to-digital converter - Google Patents

Abstract

A TWO-CHANNEL ANALOG-DIGITAL CONVERTER containing two comparison devices, two voltage dividers, in each bit, except the younger one, three coincidence elements, an OR element, two keys, two triggers, zero inputs of which are connected respectively to the outputs of the first and second coincidence elements of this the first input of which is connected to the single trigger output of the first channel of a given bit, the first INPUTS of the first and second comparison devices are connected respectively to the outputs of the first and second. voltage dividers, the first inputs of the first of which are connected respectively to the outputs of the first keys of each bit, except the youngest, and the first inputs of the second one are connected to the outputs of the BToptix keys of each bit except the younger ones, the second inputs of the comparison devices are combined and connected to the INPUT bus, and a trigger The low bit of the first channel, characterized in that, in order to increase the speed, two additional elements of a match are entered into it, and P each bit, except for the younger one, has two additional keys. The output of the first pz of which is connected to the corresponding second input of the first voltage divider, and the input to the output of the element OR of this bit, the first INPUT of which is connected to the INPUT of the first key of this bit and through the second additional key with the corresponding second input of the second voltage divider , and the second input. - with zero output of the second trigger of the given bit, the clock E1 OUT of which is combined with the clock inputs of the triggers of all the bits of the first and second channels and the OUTPUT of the first additional element with The first input is connected to the zero output (L trigger is the low-order bit of the first channel, and the second input is connected to the bus of tax impulses and the first input of the second additional coincidence element, the second INPUT of which is connected to the Start bus, and the output is connected to single trigger inputs of all bits of the second channel, a single input of a trigger of the highest bit of the first channel and zero INPUT of the trigger of the lower bit of the first channel, while the output of the first comparator device is connected to the second inputs of the first elements falling of all bits, the third INPUT of each of which is connected to the single OUTPUT of the second channel trigger, the first inputs of the second and third elements of a given bit match, the second input of which is connected to the first INPUT of the first element of a match and the second input of the second element of a coincidence bit, and OUTPUT - with a single trigger input of the first one that followed

Description

the bit, wherein the output of the second comparator is connected to the third inputs of the second coincident elements of all the bits.

The invention relates to automation and computing and can be used in digital measuring devices.

A voltage converter to a sequential approximation code is known, comprising two summation blocks, switching, comparison, control units, a source of reference voltages (currents), two registers and the connection between them LI.

The disadvantage of this converter is the low speed of the device.

Closest to the invention is a two-channel analog-to-digital converter (ADC) containing two comparison devices, two voltage dividers, in each bit, except for the younger one, three coincidence elements, an OR element, two keys, two triggers, zero inputs of which are connected respectively With the outputs of the first and second elements of coincidence of this bit, the first input of the first of which is connected to the single output of the trigger of the first channel of the given bit, the first inputs of the first and second comparison device are connected respectively with the outputs of the first and second voltage dividers, the first inputs of the first of which are connected respectively to the outputs of the first keys of each bit, except the youngest, and the first inputs of the second are connected to the outputs of the second keys of each bit, except the younger ones, the second inputs of the comparison devices are combined and The low-order trigger of the first channel i2 is connected to the input bus.

A disadvantage of the known device is also low speed.

The purpose of the invention is to increase speed.

The completed target is achieved by the fact that in a two-channel analog-digital converter, there are two comparison devices, two voltage dividers, in each category, except the younger one, three elements of a match, an OR element, two keys, two triggers, zero inputs of which are connected respectively to the outputs the first and second elements of the coincidence of this bit, the first input of the first of which is connected to the single output of the trigger of the first channel d; for this bit, the first inputs of the first and second comparison devices are connected But the outputs of the first and second voltage dividers, the first inputs of the first of which are connected respectively to the outputs of the first keys of each bit except the younger one, and the first inputs of the second one to the codes of the second keys of each bit except the younger ones, the second inputs of the comparison devices are combined and connected to the input bus, and the trigger of the lower bit of the first channel, two additional elements of coincidence are introduced, and in each category, except the younger one, two additional keys, the outputs of the first of which are connected to the corresponding second the first divider of the voltage, and the input - with the output of the OR element of the given bit, the first input of which is connected to the input of the first key of the given section and through

A second additional key — with a corresponding second input of the second voltage divider — and a second input with zero output of the second channel trigger of a given bit, the clock input of which is combined with the clock inputs of the triggers of all the bits of the first and second channels and the output of the first additional coincidence element, the first the input of which is connected to the zero output of the low end trigger of the first channel, and the second input to the clock pulse bus and the first input of the second additional coincidence element, the second input of which oedinen with. Start, and the output with single inputs of triggers of all bits of the second channel, single input of the high bit trigger of the first channel and zero input of the low bit trigger of the first channel, while the output of the first comparison device is connected to the second inputs of the first matching elements of all bits the third input of each of which is connected to the single output of the trigger of the second channel, the first inputs of the second and third match elements of this bit, the second input of which is connected to the first input of the first element tim and the second input of the second element of the discharge matcher and an output - with a single trigger input of the first channel subsequent discharge, the output of the second comparator device is coupled to the third inputs of second elements matcher all bits. Figure 1 shows the functional scheme of the proposed ADC; Figure 2 shows diagrams explaining his work. Dual-channel A1Sh contains devices and comparisons, dividers and voltages, p-bits, each bit of which, except the youngest, contains the keys,, and, triggers and, elements 5-7 matches, the element OR 8, and the youngest one d - trigger, start bus 9, clock pulse bus 10, input bus 11, elements 12 and 13 of coincidence. In the first and second channels, the first inputs of the device and the comparison are connected respectively to the outputs of the dividers and the voltage of the inputs of which are connected in each category, except the youngest, to the outputs of the keys,, and, the zero inputs of the trigger and are connected respectively to the outputs of the elements 5 and 6 coincidence of this bit, the forward and second inputs of which are connected to the first and second inputs of the matching element 7, the direct output of the trigger 4-1 of each bit is connected to the input of the element OR 8. Bus 9 Start, bus 10 clock pulses, input bus 11 are connected soo respectively to inputs of the coincidence element 12, and comparing element 13 matcher. Dual-channel ADC works as follows. Clock signals are continuously applied to clock bus 10. The commencement of one cycle of converting voltage to code is to apply a signal to bus 9 Start. The clock signals and the start signal go to the inputs of the element 13, which forms the trigger setup signal and to the initial state. In the initial state, all the triggers of the second channel and the trigger of the higher bit of the first channel are set to one, the remaining triggers of the first channel are set to the zero state. When installing the lowest-order trigger of the first channel to the zero state, the unit potential at the zero output allows the passage of clock signals from bus 10 through element 12 to the clock inputs of all the triggers and. In the initial state of the triggers, the compensation voltage generated at the output of the divider of the first channel and supplied to the first input of the device of the first channel is 2/3 of the scale of the voltage generated, and the compensation voltage generated at the output is div. bodies of the second channel and supplied to the first input of the device of the second channel, equal to 1/3 of the scale generated by the voltage divider. The voltage to be converted comes from the input bus 11 to the second inputs of the devices and the first and second channels. The device forms permitting (single) signals at its output, provided that the compensating voltage from the divider is greater than the voltage to be converted, and the device is provided that the converted voltage is more than the compensating voltage from the divider. Depending on the ratios of the converted and two compensation voltages at the inputs to the device, and enabling signals appear at the output of one or the other or at both outputs simultaneously, which are fed to the third inputs of elements 5 and 6. Single signals from the single outputs and the flip-flops and the first the bits of the first and second channels go to the first and second f1 inputs of elements 5-7 of the first bit. At the output of element 7, a single signal is generated. At the outputs of element 5, single signals are formed under the condition that there is a single signal at the third input from the device, and at the output of element 6, under the condition that there is a single signal from the output of the device, the signals from elements 5 and 6 of the first bit change state triggers are the first time in a row when there is a clock signal, and the signal from element 7 of the first bit changes the state (if there is a clock signal) from zero to one trigger of the second bit of the first channel. Since the pair of triggers of the first row is in the 1 1 state and the enabling signals from the outputs of elements 5 and 6 are fed to the zero inputs of the triggers and this bit, one of the triggers or both switch to the zero state on the clock edge. the three second-stage gers are in the state: the trigger of the first channel is at zero (0): the trigger of the second channel is in the unit (1), t, e, the pair is in the state 01, and the lower and lower bits are the same state 01, formed at the output of the element 7 of the first bit a single signal aets per unit second input trigger discharge of the first channel. According to the clock front, simultaneously with switching of a pair of flip-flops and the first bit, three germs of the second bit of the first channel are also switched, and thus a pair of second-bit flip-flops are switched from state 01 to state 11, Since a pair of triggers and a second bit And even the pairs of flip-flops and the remaining low-order bits were up to the clock edge in state 01, then no element 7 of the remaining bits generates enabling signals for switching the next bit triggers of the first channel to unit state T In this way, the analysis of the ternary state of the first discharge, the recording of this ternary state in a pair of trigger and the first bit, and, setting the pair of triggers and bit 10 to state 11, takes place in one cycle, while state 11 is measuring, The states of pairs of triggers 01, 00, and 10 indicate one of the three numbers of the ternary digit: O, 1 or 2. The operation of the converter when detecting the state of each subsequent ternary digit is similar, with the only difference: the pair of triggers of the higher bits, in which already recorded ternary states and 01, 00 or 10, block the formation of enabling signals at the outputs of elements 5-7 of these high-order bits and, therefore, exclude the possibility of repeated failure of these bits. The states of a pair of triggers of the same discharge form levels of voltages (currents) at the inputs of the digits of the dividers and. When a zero signal is applied to the input of keys,, and there is a low potential (or zero current) on their outputs, and when a single signal is given, a high potential (fixed current) is present. When a pair of flip-flops 01 is on, the flip-flop output of the first channel is zero the signal at the zero output of the trigger 4-2 of the second channel is also a zero signal, these zero signals are sent to the key inputs, and directly to the key input through element 8, Since when the zero signals are applied to the key inputs, and their outputs are present low potentials (absence), then a low potential is applied to the input of this bit of the divider. When the pair of flip-flops 10 is on, the single trigger output of the first channel and the zero trigger output of the second channel have single signals, these single signals are also fed to the inputs of keys 3-1, 3-2 and 3-4 directly and to the input of key 3-3 through element 8. Since, when single signals are applied to the inputs of the discharge keys, high potentials are present at their outputs (the presence of currents from all the keys), a high potential is applied to the input of this bit of the divider. When the pair of flip-flops 00 is on, the single output of the first channel trigger has a zero signal, and the single signal has a single signal at the zero output of the second channel trigger. In accordance with this, zero signals are supplied to the inputs of the keys and zero signals are present at their outputs. Single signals are sent to the input of the key directly and the key through element 8, whereby there are high potentials at their outputs. Since the outputs of the keys and are connected to the input of this bit of divider 2, an average potential is formed at the divider node. Similarly, from the outputs of the keys 3-2 and 3-4, connected to the input of the discharge divider, the average potential (average current) is also formed in the divider node. In the measuring state, a pair of flip-flops 11 on the unit output of the first channel trigger has a single signal that goes to the inputs of keys 3-1 and 3-2 directly and to the key input via element 8. These keys form high potentials at their outputs. At the zero output of the trigger of the second channel register there is a zero signal, which is fed to the input of the key 3-4, and at the output of which a low potential is formed. Since the keys are connected to the bit inputs of the dividers and in a certain way, in the measuring state a high potential is supplied to the bit unit of the divider, and the average potential is sent to the bit unit of the divider. The initial state of the trigger pairs for the first bit 11, i.e. measuring, for the remaining bits 01 (ternary O). In accordance with VII with this, signals that are represented by the ternary code 200 O are given to the inputs of the keys and bodies connected to the bits of the bits, and a voltage equal to 2/3 of the maximum potential voltage generated is generated at the output of the divider. . Signals that represent the ternary code 100..O (where 1 and 2 are equivalents to the number of keys 3, at the outputs of which there is a high potential) are supplied to the inputs of the keys and connected to the bits of the divider, and a voltage is generated at the output of the divider equal in amplitude to 1/3 of the maximum possible generated voltage. The voltage to be converted from the input 11 to the second inputs of the device is compared with the compensating voltages from the dividers and. If the converted voltage is lower than 1/3 of the voltage scale, then a single signal is formed at the output of the device, and through element 5, the trigger of the first channel is set to the zero state, i.e. the trigger pair becomes state 01 (ternary O). If the converted voltage is in the range of 1/3 to 2/3 of the voltage scale, single signals are formed at the outputs of the devices and, through elements 5 and 6, the pair of triggers of the first discharge is set to the state of 00 (ternary 1) . If the converted voltage exceeds 2/3 of the voltage scale, then a single signal is generated only at the output of the device, and through element 6 on the front of the beat of the pair of triggers and the first bit is set to state 10 (ternary 2). In whatever state a pair of triggers of the first bit is set, the triggers of the pair of the second bit are set to the measuring state by the first clock. In the second conversion step, the signals are input to the inputs of the keys and connected to the bit divider, which can be represented by the ternary code X20..0, and the bit divider by the code X10..0. Thus, in the second cycle, a third of the voltage scale, selected in the first cycle, and defined as X, is again divided into three parts by the generated voltages, each 1/9 of the voltage scale, devices and form the corresponding single signals by analogy the work in the first cycle and on the front of the second clock signal of the trigger pair in the second bit is set to the required state, and the pair of the third bit triggers is set in the measuring state. Work on subsequent cycles in tact is similar to the one considered. When determining the state of the next-to-last bit, switching on the single input of the three bits of the last bit of the first channel is prepared, and on the front of the clock signal there is a corresponding switching. The trigger of the last bit of the first channel switches to state 1, a zero signal appears at its zero output, which blocks the passage of clock signals from bus 10 through element 12 to the trigger inputs and, and the conversion stops, the last ternary state displayed at the outputs of the devices and or neither of the outputs of elements 5 and 6 of the last bit. The total number of clock cycles (start-up cycles) is equal to the number of tooic bits of the converter. Thus, the proposed converter reduces by 1.5 times the number of clock cycles for the conversion, not the introduction of more high-speed elements into the circuit, since for eleven bits of the converter (at 2 2048 coding gradations), in known solutions, in the proposed solution (with 3,287 coding gradations), at the threefold bits of the converter, the entire conversion cycles are required. In this case, in a known solution, a trigger is required for constructing a converter, in the proposed solution of triggers.

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Claims (1)

A TWO-CHANNEL ANALOG-DIGITAL 'CONVERTER containing two comparison devices, two voltage dividers, in each category, except the lowest, three coincidence elements, an OR element, two keys, two triggers, the zero inputs of which are connected respectively to the outputs of the first and second coincidence elements this time series, the first input of the first of which is connected to the single output of the trigger of the first channel of this discharge, the first inputs of the first and second comparison devices are connected respectively to the outputs of the first and second. voltage dividers, the first inputs of the first of which are connected respectively with the outputs of the first keys of each category, except for the lowest, and the first inputs of the second are with the outputs of the second keys of each category, except for the lowest, the second inputs of the comparison devices are combined and connected to the input bus, and the trigger of the least significant the first channel, characterized in that, in order to improve performance, two additional matching elements are introduced and in each category, except for the lowest, two additional keys, the output of the first of which is connected to the corresponding second input of the first voltage divider, and the input with the output of the OR element of this discharge, the first input of which is connected to the input of the first key of this discharge and through the second additional key with the corresponding second input of the second voltage divider, and the second input is with the zero output of the trigger the second channel of this category, the clock input of which is combined with the clock inputs of the triggers of all bits of the first and second channels and the output of the first additional matching element, the first input of which is connected to zero exit | low-order flip-flops of the first If channel, and the second input - with the clock bus U and the first input of the second additional matching element, the second input of which is connected to the Start bus, and the output - with the single inputs of the triggers of all bits of the second channel, with a single input of trigger * of the highest order of the first channel and zero input of the trigger of the least significant of the first channel, while the output of the first comparison device is connected to the second inputs of the first elements of coincidence of all bits, the third input of each of which is connected n with a single output of the trigger of the second channel, the first inputs of the second and third matching elements of this category, the second input of which is connected to the first input of the first matching element and the second input of the second matching element of this category, and the output is with the single input of the trigger of the first channel of the subsequent discharge moreover, the output of the second comparison device is connected to the third inputs of the second elements of coincidence of all bits.