SU661815A1 - Frequency divider - Google Patents

Description

one

The invention relates to a pulse technique.

A pulse frequency divider is known that contains a shift register consisting of N memory elements, two logical elements NOT and "exclusively OR, and a logical element" exclusively OR NOT connected respectively to bits of shift register 1.

The disadvantage of such a divider is its complexity.

The closest to the technical nature of this invention is a frequency divider containing four bits each of which contains a memory trigger and two switching triggers, the first inputs of each of which are connected to the input thickness, the output of the first switching trigger of the first bit is connected to the second the inputs of switching triggers of the second and third bits and the second input of the second switching trigger of the fourth discharge, the output of the first switching trigger of the second discharge is connected to the third and fourth With the third inputs of the third switching trigger of the third bit, the output of the first switching trigger of the third bit is connected to the third and fourth inputs of the second switching trigger of the fourth bit 2.

The disadvantage of this divider is insufficient stability with a division factor of 6, 5.

The aim of the invention is to increase the stability of the division ratio.

The goal is achieved by the fact that a frequency divider containing four bits connected in series, each of which contains a memory trigger and two switching triggers, the first inputs of each C9 are connected to the input bus, the output of the first switching trigger of the first bit is connected to the second inputs switching triggers of the second and third bits and the second input of the second switching trigger of the fourth discharge, the output of the first switching trigger of the second discharge is connected to the third and fourth th inputs of the second switching trigger the third discharge, the switching output of the first flip-flop of the third discharge connected to the third and fourth inputs of the second flip-flop of the fourth switching discharge, introduced an additional

the logical element AND-NOT, the inputs of which G. COieaHHeTibi with the outputs of the second commutation. the fourth trigger, the unit output of the first switching trigger of which is connected to the auxiliary input of the first switching trigger of the second discharge, and the unit output of the second switching trigger of the fourth discharge is connected to the auxiliary input of the first switching trigger for the first time and the second additional input of the first switch. bit

The structural electrical circuit of the proposed divider is shown in the drawing. The divider contains four bits 1–4, each ftTfcoYbpbix consists of commutation triggers and one memory trigger. Switch triggers are executed on AND-NOT 5-20 logical elements, and memory triggers are executed on AND-NE 21-28 logical elements. The divider also includes an additional logical

AND-NOT element 29..

The input signal is fed to the input bus 30, the output clifHaJi i1GeTS g c iBbixo 31.

The principle of operation of the divider is

 in the following.

In the light condition, the memory bit trigger Wb6Tb of the bit is found in the cTHWHnTi COMMON, the residual bit memory triggers are in the zero state.

Under the action of Cigla in the divider, the usual recalculation of incoming pulses in binary code is carried out. With the sixth pulse count on: output: lo-. A logical element N-19 is a signal equal to a logical zero, which sets the fourth-bit memory trigger to the one state and which, via the logical one, AND-N-29 gains access to the output. Next, the usual trans-g q | 4p-tojfj Tiy g P31c drive is performed.

 - the decimal Nmpulbs and the divider is set to code 1110. After the termination of the twelfth pulse at the output of the Logic Element IS-NO 20 pb, the GLS11 is equal to the logical zero, which is black; the logical IS-NOT 29 arrives at the output. Simultaneously, the signal is equal to Gogic KOTSry yule from the output of the logic element

AND-NOT 29, nbctynSet on the DSCH61 LOGICAL

elements AND-NOT 5, 7, wherever Tiga and r in the input

there will be a signal equal to a logical one.

With the arrival of the thirteenth, the pulses open. logical elements

AND-NOT 6, 14, 18, yatTZhYy GGGbTL are

7 signals equal to logical zero, which

set the triggers of the memory of the third and fourth bits in the zero state

The first memory trigger. Trigger

M4i (-iijr; -i JSi-l.;: Bd r: v-m

memory of the second bit does not change its state, since the logical element, the IS-NOT 10 remains closed by the signal at first equal to a logical zero from the output of the logical element IS-NOT 20, and then by the signal from the output of the logical element IS-NOT 18. After the end The input signal is returned to the initial state 0010.

Thus, by 13 input pulses, the divider produces two output, i.e., frequency is divided into 6, 5, and the output signals are formed at equal time intervals. In addition, the divider allows frequency division

at 13, the output signal is the signal from the output of the logical element NONE 19 or NONE 20.

Claims (2)

1. The patent of France No. 2105319, cl. H 03 K 23/02, 02.06.72. five 2. USSR author's certificate number 561299, CL. NOZ K 23/02, 1977.