SU1228268A1 - Counting device - Google Patents

Abstract

The invention relates to computing and discrete automation and can be used to count pulse signals. The purpose of the invention is to simplify the device. The device contains a clock bus I, counter 2 and counting bits 3-1-3-p, each of which includes RS-flip-flops 4,5 and 6, the First input of the OT-flip-flop 5 of each counting bit is connected to auxiliary Set and reset inputs for RS-flip-flop 4 of the next bit. 1 il. (L J too 00 ND 05 00

Description

The invention relates to digital computing and discrete automation and can be used to count pulse signals.

The purpose of the invention is to simplify the device.

The drawing shows a block diagram of the proposed counting device.

The counting device contains a clock bus 3, the counter 2 and the countable bits) - (3-p), each of which contains the first 4, second 5 and third 6 PZ-flip-flops, the first output of the first H8 - trigger 4 is connected to the input setting the second RS flip-flop 5, the second output of which is connected to Ehod1 and resetting the third 6 and the first 4 short-circuits of the third RS-TpHrrepa 6 is connected to the installation input of the first RS-flip-flop 4, the second output of which is connected to the installation input Third EB-trigger 6, the first additional reset inputs of the first 4 and second 5 RS-flip-flops are connected with the first clock input of this counting bit, the second clock input of which is connected to the second auxiliary inputs of the first reset of the first 4 and second 5 RS flip-flops, nepBbje clock inputs of the counting bits {3-l) - (3-n) are connected to the clock bus 1 and the counter input 2j, the output of which is connected to the second clock inputs of the digit bits (() 5, the first output of the second RS flip-flop 5 of each digit bit is connected to the auxiliary inputs of the installation and reset the first RS trngger 4 pgogo Yes.

When using triggers with in- EepCHbHsai set and reset inputs B, the direct and inverted OUTPUTS are used as the first and second outputs of the triggers; and when using triggers with direct install and reset inputs, inverse and direct outputs.

The counting device works as follows

The state code of the counting device is removed in the first k-bits from the outputs of counter 2, and in bits from the (k-Hl) th software () -th from the first three third trigger points, 6 bits 3-n, respectively (k - - the number of bits of the counter 2).

28268a

Counter 2 generates a carry signal a. P-1 only for every 2 pulse on bus 1; In this case, the transfer signal P switches in pause

5 between pulses on the bus 1.

Consider the operation of the counting device from the initial state of logical units at the skew output and the outputs of the k-bits of counter 2 and

 On the first outputs of bits 3-25, ..., 3-p. The front of the first pulse on bus 1 switches to a logical zero signal: ala at the outputs of the k bits of counter 2 and B logical unit - 5 signals at the output of the first bit 3- (at the direct output of flip-flop 6). On a slice of the first pulse and bus 1, the signal is switched to a logical zero. at the output of the transfer P of counter 2

20 and on the first trigger 4 of the first bit 3-lg, after which the signal at the first output of the second trigger 5 of the first bit 3-1 is switched to a logical unit. then, in the log, 5 cc zero is the signal at the output of the first VOGS1 trigger 4 of the second bit 3–2, after which the signal at the output of the second trigger 5 of the second bit 3–2 switches to the logical:

30, etc. Then, the signals at the output of the first flip-flop 4 are sequentially switched to a logical zero and at the first output of the second flip-flop 5 n-th bit 3-n to a logical unit of the TC. For the counter to work correctly in the control mode with maximum speed, it is necessary that the last switch occurs before the front of the 2nd pulse in chic I. This

4Q corresponds to the condition 2n-6-2-3, and 2i-n ™ 2: -0.

From here it is necessary to choose the parameters n and K. For example, for a 12-bit counter and a device to

4fi 25 bits can be built with.

Although the transfer is organized sequentially in p-bits, the device operates in a control mode with a minimum clock period of 6t: which is determined by the type of bit used, where tg is the maximum delay of the used logic elements.

35,

Claims (1)

Invention Formula A counting device containing a clock bus ,, counter and counting times3 Rows, each of which contains the first, second and third RS-flip-flops, the first output of the first RS-flip-flop is connected to the installation input of the second RS-flip-flop, the second output of which is connected to the reset inputs of the third and first ES-flip-flops, the first output of the third The RS flip-flop is connected to the setup input of the first RS flip-flop, the second output of which is connected to the setup input of the third RS flip-flop, the first additional reset inputs of the first and second RS flip-flops are connected to the first clock input given the second counting bit, the second tact is 15 bits. The input of which is connected to the second additional reset inputs of the first and second RS flip-flops, the first clock inputs of the counting bits are connected to the clock bus and the counting input of the counter, the transfer output of which is connected to the second clock inputs of the counting bits, characterized in that simplify the device, the first output of the second RS-flip-flop of each counting bit is connected to the auxiliary inputs of the installation and reset the first RS-flip-flop of the next