SU907809A1 - Device for monitoring operation of synchronous automatic machine - Google Patents

Description

one

The invention relates to automation and computing and can be used to control the operation of digital devices.

A device for controlling a counter is known, which contains a block of decoders, a counter and an analysis block l.

The disadvantage of this device is the insufficient depth of control.

A device for controlling a counter is known, which contains a counter, two groups of inputs, a decoder of allowed combinations, an analysis unit and a block of differentiating circuits, the first group of inputs is connected to the inputs of a block of differentiating circuits and outputs of the counter, the outputs of the block of differentiating circuits are connected to the inputs of the decoder of allowed combinations, the output of which is connected with the first input of the analysis unit, the second input of which is connected to the clock bus.

During operation, the decoder of the allowed signal combinations periodically switches the trigger in the analysis circuit. Clock signal toggles. another trigger. If the state of the triggers is not equal, then this indicates the presence of a scheduling counter.

A disadvantage of the known solution is the low depth of control.

The purpose of the invention is to increase

10 depth control.

The goal is achieved by the fact that the device for controlling the operation of a synchronous automaton containing two groups of inputs, the decoder is allowed 5 signal combinations and the analysis unit, the first and second inputs of which are connected respectively to the output of the decoder of allowed signal combinations and the clock bus

20 block of delay elements, block of signal generators of the derived alphabet, and block of forming tuning signals, the first group of inputs is connected to the first group of 5l. inputs of blocks of signal generators of the derived alphabet and generation of tuning signals and with inputs of a block of delay elements, the outputs of which are connected to the second group of inputs of the block of signal conditioners of the derived alphabet, the third group of inputs of which are connected to the first group of inputs of the decoder of allowed signal combinations and settings, the second group of inputs of which is connected to the second group of inputs, the second group of inputs of the decoder of the combined combinations of signals price per unit output of the derivative signal alphabet. FIG. 1 shows a block diagram of a device for control together with a control object — a synchronous automaton; figure 2 - diagram of the control operation of the reversible counter. The device contains a block .1 elemen LLP delay, block 2 signal formers of the derived alphabet, a decoder 3 allowed signal combinations, an analysis unit, a block 5 of shaping tuning signals, output bus b, synchronous machine 7, clock bus o, first tire group 9 and second ShKCh group 10. Bus group 9 is connected to r, the first bus group of the tuning signal generation unit 5 and the control inputs of the synchronous automaton 7, the outputs of the components of the internal states of which are connected to the bus group 10, which is connected to the second input group block 5 of forming signals with the first group of inputs of block 2 of signal formers of the alphabet GENERATED and inputs of block 1 of delay elements, the outputs of which are connected to the second group of inputs of block 2 of signal formers of the derived alphabet, the third group of inputs of which are connected with the outputs of block 5 of signal formers settings and with the first group of inputs of the decoder 3 allowed combinations of signals of the second group of inputs and the output of which are connected respectively to the outputs of the block 2 of signal conditioners pro of the alphabet and with the first input of the analysis unit 4, the second input of which is connected to the clock bus 8 (the clock input of the synchronous machine 7, the output of the analysis unit is connected to the output bus 6. The analysis unit may contain, for example, the elements AND and the delay element. Block 2 of derived alphabetic signal conditioners contains bit-wise combinational logic circuits whose task is to calculate a certain logical function of the current and delayed components of the internal state vectors of the synchronous automaton 7 Depending on the input signals on the EY 10 bus groups, each bit has a combinational logic circuit in block 2, together with the corresponding delay element in block 1, performs the function of, for example, a differentiating chain that reacts to the re-IIQII H II. or 3 allowed signal combinations, tunable by the tuning signal generating unit 5, reacts to the appearance of allowed pulse combinations at the output of block 2. The analysis block k emits an error signal 8 if there is no signal for the allowed combination at the output of block 3 and there is a signal on bus 8 The tuning signal shaping unit 5 generates the control signals for block 2 and decoder 3 so that their tuning corresponds to the maximum possible depth of control. The device works as follows. When switching a synchronous machine 7, pulse combinations occur at the outputs of block 2 of the signal drivers of the derived alphabet, corresponding to the correct operation of the control object. In the case of a failure, the forbidden signal combination is detected by the decoder 3 allowed signal combinations. The analysis unit is periodically cocked with a clock signal from bus 8 and zeroed by the signal from the output of the decoder 3 allowed signal combinations. If zeroing does not occur, the analysis block counts to two and gives an error signal. FIG. 2 and as an example, the control circuit of the reversible counter operation is given. All the blocks corresponding to the blocks of the generalized structure, in FIG. 1 circled and marked with the same numbers. As the formers of the signals of the derived alphabet, which are part of block 2, a modulo two controllable cell is used. A variant of its specific implementation is shown in Fig. 26. The block 5 of the tuning signal formers contains, respectively, de-encoders 11 zeros and 12 ones, elements NOT 13 and k, elements AND 15-1 and elements OR 18-19. The busbar group 10 is connected to the inputs of the decoders 11 and 12, the output of the first of which is connected to the first inputs of the elements AND 15 and OR 19, the second input of which is connected to the output of the element And 17, the first and second inputs of which are connected respectively to the bus 9 and c the output of the element NO 1, the input of which is connected to the output of the decoder 12 units and the first input of the element 16, the second input of which is connected to the bus 9 and to the input of the element HE 13, the output of which is connected to the second input of the element 15 and whose output is connected to the first input element OR 18, the second input is pogo connected to the output element And 1b. The device diagram also contains the elements NOT 20-22, the elements AND 23 and -24, the element OR 25 and the first 26, the second 27, the third 2b inputs of the signal bodies of the derived alphabet of the block 2 16). If 1 is present at input 28, the drivers are configured to switch the counter bits from O to 1, otherwise from 1 to O. The decoder 3 allowed signal combinations produce a single output signal in two cases: if the states of all counter bits and if the state of only one bit changes. The setup of the decoder 3 for each of these cases is made by the block 5. of forming the tuning signals. The analysis unit k is a two-bit counter which is periodically cocked and zeroed by a clock signal from bus 8 and a signal from the decoder 3 of the allowed signal combinations. The tuning signal generating unit 5 is a combinational machine with two control outputs (outputs of the elements OR 18 and 19), which generates tuning signals depending on the INPUT signal and the internal state of the counter. The minimum and maximum counter codes are fixed by decoders of 11 zeros and 12 ones. Due to the flexible adjustment of the control device blocks, it is possible to achieve the maximum control depth at each step of the operation of the machine. As a result, all control of the machine has the greatest depth. Therefore, the detecting ability of the device proposed is substantially higher than the detecting ability of a known solution. The advantage of the proposed solution is that it is suitable not only for autonomous machines, but also for machines of a general form. Claim of the invention A device for controlling the operation of a synchronous automatic machine, comprising two groups of inputs, a decoder of allowed signal combinations and an analysis unit, the first and second inputs of which are connected respectively to the output of the decoder of allowed signal combinations and a clock bus, characterized in that, in order to increase the depth of control, A block of delay elements, a block of signal generators of the derived alphabet, and a block of forming tuning signals are entered into it, the first group of inputs is connected to the first groups of input in blocks of shapers of derived alphabet and forming tuning signals and with inputs of a block of delay elements whose outputs are connected to the second group of inputs of a block of shapers of derived alphabet, a third group of inputs of which are connected to the first group of inputs of the decoder of allowed signal combinations , the second group of inputs of which is connected to the second group of inputs, the second group of inputs of the decoder of allowed signal combinations is connected with outputs of the block of signal conditioners of the derived alphabet. Sources of information taken into account in the examination 1. USSR author's certificate number 416883, cl. H 03 K 21/3. 197. 2. USSR author's certificate number ZBZU b, cl. H 03 K 21/3. 1972 (prototype).

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Claims (1)

Claim A device for monitoring the operation of a synchronous automatic machine, containing two groups of inputs, a decoder of allowed combinations of signals and an analysis unit, the first and second inputs of which are connected respectively to the output of the decoder of allowed combinations of signals and a clock bus, characterized in that, in order to increase the depth of control, it a block of delay elements, a block of signal generators of the derived alphabet and a block of formation of tuning signals are introduced, the first group of inputs is connected to the first groups of inputs of the blocks of the generator th signals of the derived alphabet and the formation of tuning signals and with the inputs of the block of delay elements, the outputs of which are connected to the second group of inputs of the block of shapers of the derivatives of the alphabet, the third group of inputs of which is connected to the first group of decoder inputs of the allowed combinations of signals and the outputs of the tuning signals generating block, the second the group of inputs of which is connected to the second group of inputs, the second group of inputs of the decoder of allowed combinations of signals is connected to the outputs of the unit firs derivative alphabet signals.