SU1010717A1 - Pseudorandom train generator - Google Patents

Abstract

GENERATOR OF PSEUDICAL SEQUENCES, containing a clock pulse generator, the output of which is connected to the first input of the shift register, the kth and nth outputs of which are connected, to the inputs of the half-adder, the pth output of the shift register is connected to the first input of the I element, the second input of which is connected to the trigger output, the first input that is connected to the output of the pulse counter, the switch and the programming unit | 1 ||, which is different in order to increase its reliability 1: and, in series, the n-bit connected semi-adder and multi-input element And, the output of which is connected to the second input of the trigger and the first input of the pulse counter, the second input of which is connected to the output of the generator, the torus of clock pulses, the first group of inputs of the n-bit half-crusher connecting to the outputs of the shift register, and the second group of inputs connected to the outputs of the program setting block, while the output of the half-adder is connected to the third input of the element I, the output of which is connected via a switch to the second input of the shift register and the output of the half-adder.

Description

yy

tk

/.

r :: :)

G4G

6

/

t

ff. ff The invention relates to a pulse technique and can be used as a source of test signals for measuring the error rate in equipment of digital information transmission systems. A pseudorandom sequence generator (PRS) is known, which generates a pulse generator, a pulse counter, a trigger, and AND elements. However, in this device it is impossible to generate a sync signal at any segment (SRP). Closest to the proposed technical entity is a pseudo-random sequence generator containing a clock pulse generator, a linear feedback shift register, a counter, a short-circuit trigger, a coincidence element, a switch switch, and a counter with an adjustable count factor. The device generates a memory bandwidth and code words. The pulses from the clock generator are fed to the shift register, and through the switching device to the counter with the MiJM regulating counting factor. Register dvd, yoke forms the bandwidth. At the same time, a counter with an adjustable counting factor begins to count clock pulses arriving at its input 2, however, the known device does not allow to quickly form the structure of the code word and does not provide reliable operation when resetting the register, and also does not allow to form sync on any of the PSP sections . The purpose of the invention is to increase the reliability of the device. The goal is achieved by those in a pseudo-random sequence generator containing a clock pulse generator whose output is connected to the first input of the shift register, the kth and nth outputs of Kotoporo are connected to the inputs of the half adder, the nth input of the shift register is connected to the first input of the element And, the second input of which is connected to the trigger output, the first input of which is connected to the output of the pulse counter, a switch and a block h: a program, introduced in series connected n-bit half-adder and a multi-input element Ient, whose input is connected to the second input of the trigger and the first input of the pulse counter, the second input of which is connected to the output of the clock generator, the first group of inputs of the n-bit half-adder is connected to the outputs of the shift register, and the second group of inputs is connected to the outputs of the task unit the program, while the output of the half adder is connected to the third input of the element I, the output of which is connected via a switch to the second input of the shift register and the output of the half adder. The drawing shows a block diagram of the generator PSP. The SRP generator contains a generator of 1 clock pulses, a shift register 2, a program setting block 3, a p-bit semi-adder 4, a multiple-input element And 5, a semi-adder 6, And 7, a switch 8, a trigger 9, a counter 10 pulses, in which the coefficient can be rearranged recalculation, the output bus 11 and the bus 12 clock pulses. The device works as follows. The generator, depending on the position of the switch 8, can be in two operating modes: in the memory band mode and in the code word mode. In the PSP mode, the generator operation corresponds to the operation of the known PSP generators. In this case, the semi-adder b | is connected to the input of register 2 with its output. In the mode of forming the code word, the element AND 7 controlled by the trigger 9 connects the input of the register 2 or with the output of the semi-adder 6, in the case of BTO, in the register 2 th bit of register 2, while in the register 2 the p-bit segment of the bandwidth that was in register 2 at the time of switching the feedback circuit continuously circulates. Trigger 9 changes its state at the moment when the n-bit PSP segment coincides with the n-bit code word set in block 3. Such a coincidence will always occur once per PSP period, since in it with a length of character periods contain any n-bit combinations (except the combination 000 ...). At the moment of coincidence, logical units appear at the p outputs of half adder 4, and a pulse is formed at the output of element 5 and sets the following: trigger 9 to the position where, through element 7, the output of the nth register bit 2 is connected to the input of register 2. In this mode, after every p clock, the generator generates an n-bit word, the structure of which is specified by block 3, and after every n clock cycles at the input of the AND 5 element, a coincidence clock repeats. When changing the structure of the word, the sync signal on bus 12 disappears, since the new typed word circulating in register 2 no longer matches, and the signal goes through the clock at the output of counter 10. the translating trigger 9 to the opposite state, in which the output of the half-adder 6 through the element 7 is connected to the input of the register 2, i.e. The generator will switch to the memory bandwidth mode. After this word, the sync signal on bus 12 will occur when the typed code word coincides with the corresponding memory bandwidth, the count 10 is set to zero, and the trigger 9 is set to the state corresponding to the word mode. In the proposed device B of the memory bandwidth mode, a sync signal is generated at any selected part of the sequence up to the clock. This sync signal is formed using a half-adder 4 connected to the shift register 2 and block 3, the outputs of which are combined by the AND element 5. Depending on the typed combination, in block 3 a sync signal will be generated corresponding to the part of the sequence generated in register 2 of the shift. The auxiliary frequency F and the capacitance of the counter 10 N are chosen so that at the output of the counter 10 after the clock pulse disappears, it appears after a time longer than the period of the sequence. Thus, in the proposed generator, in comparison with the known ones, the reliability is improved due to the fact that when the shift register is zero and the synchronization is lost, the generator is translated into a memory banding mode containing all types of code words that can be typed using the program setting block. When forming a code word, the output of the shift register automatically closes at the input when the contents of the shift register in which the memory bandwidth is generated coincides with the specified code word structure and therefore after switching this code word continues to be periodically generated at the output of the shift register, this is the output of the device.

Claims (1)

Pseudo-random sequence generator, containing a clock pulse generator, the output of which is connected to the first input of the shift register, the kth and nth outputs of which are connected, to the inputs of the half-adder, the n-th output of the shift register is connected to the first input of the element And, the second input of which is connected to the output of the trigger, the first input of which is connected to the output of the pulse counter, a switch and a program setting unit, characterized in that, in order to increase its reliability, serially connected half-bit half-sums are introduced into it op and a multi-input element And, the output of which is connected to the second input of the trigger and the first input of the pulse counter, the second input of which is connected to the output of the generator, the torus of clock pulses, the first group of inputs of the η-bit half-adder connected to the outputs of the shift register, and the second group of inputs connected with the outputs of the program task block, while the output of the half-adder is connected to the third $ input of the And element, the output of which ί is connected through the switch to | the second input of the shift register and you- | half adder. I