SU951301A1 - Pseudo-random code generator - Google Patents

Description

The invention relates to computing and can be used to organize probabilistic tests of digital objects; for obtaining sequences of random codes of a given weight, necessary for the computer synthesis of control tests; to form pseudo-random symbol sequences, as needed. during statistical modeling of physical processes and the synthesis of probabilistic automata.

A generator of uniformly distributed pseudo-random numbers is known, containing shift registers with modulo-two adders in the feedback circuit til.

The disadvantage of this generator is that it does not have the ability to change the probabilities of the signals at its outputs.

Also known is a controlled random or pseudo-random sequence generator, which contains a random pulse sensor, connected to the input of the shift register, a clock generator, a counter, the inputs of which are connected to the inputs of the decoder connected to the output

input to the dial pad connected to the switch matched circuits. The disadvantage of this generator is the high hardware costs (dial panels, decoders, com-mators, matrix rip mutators, etc.). In addition, the use of such a generator as a source of verification codes in control systems

10 complex digital circuits have significant limitations due to the fact that for a larger class of digital circuits, the fronts of signals on a certain number of input

15 poles leads to the so-called fronts race, as a result of which it is impossible to determine the unambiguous state accepted by the circuit. Indefinite behavior of the choke.

20 makes it difficult to reliably assess its correct functioning. For a known generator, any combination of output signals can appear at its outputs and, accordingly, a simultaneous switching (change of states) of an arbitrary number of outputs can occur simultaneously, which, as noted, is a significant disadvantage for test sequence generators.

30 The closest technical solution to this invention is a pseudo-random code generator containing a shift register with modulo two adder in a feedback circuit, a controlled shift register, each bit of which contains a trigger, the first, second and third elements and the OR element , the unit specifying the code weight Ez 3. The known device allows obtaining on each output various pseudo-random sequences, and the probability of occurrence of a single character in each sequence can be changed from a given when used as a source of test sequences in the generation process, combinations of output signals may occur, at which a simultaneous random change of two or more signals at the inputs of the test circuit occurs, resulting in a test circuit that can assume an undefined state. Moreover, for it, the generation rate depends on the number of generator outputs, significantly decreasing With increasing, the number of outputs. The purpose of the invention is to expand the functional capabilities of the generator by obtaining sequences of pseudo-random signals with predetermined phantom ratios, as well as increasing the speed of the generator; To achieve this goal, a well-known pseudo-random code generator, containing an M-sequence generator, the first group of outputs of which is connected to a group of inputs of a controlled shift register, the control input of which is connected to the output of a code weight setting unit, the first input of which is a control input the generator, the clock input of which is connected to the clock inputs of the M-sequence generator and the controlled shift register, the output of which is connected to the second input of the code weight setting block, are entered p / flip-flops and p-decoders, the control inputs of which are connected to the output group of the controlled shift register, respectively, the outputs of the second, third, ..., 1st) groups of the M-sequence are connected to the corresponding inputs of the first, second, ... , p-th decoders, the outputs of each i-ro (, 2, ... n) of the decoder are connected to the counting inputs of the corresponding 1151х triggers of the i-th group, the outputs of which form the i-th group of generator outputs. Figure 1 shows the block diagram of the generator; FIG. 2 is a control circuit of the shift register; FIG. FIG. 3 block diagram: assigning a code weight. The generator contains the generator M of sequence 1, the outputs of which are divided into 1 groups of m bits each. The outputs of each group of block 1 are connected to the inputs of one of 1 decoders 2. A control input 3 of each of decoders 2 is connected to one of 1 outputs of a controlled shift register 4. Each of 1-2 outputs of all decoders 2 is connected to a counting input one of the 1-2 output triggers 5, the outputs of which are outputs of the generator. The inputs of the controlled shift register 4 are connected to 1 arbitrary outputs of block 1. The output 7 of the last discharged shift register 4 is connected to one input of the weight setting block 8, the second input of which is connected to the tuning bus 9, and the output of which is connected to input 10 the first bit of the controlled shift register 4. The clock signal 11 is connected to the clock inputs 12. and 13 of blocks 4 and 1. The controlled shift register 4 (FIG. 2) contains the triggers 14, elements 15-17, and the IDN element 18 This block performs the functions of a probabilistic switch, which in the tea order predetermined number deshifratorov.2 connects to the outputs of the random number generator unit 1. The essential point is that to provide varying probability of occurrence of the unit signal on any of the. Outputs b of the proposed generator are very convenient to use for building block 4 a control shift register. When the number of units (the code weight) circulating in the controlled shift register changes, the selection frequency of each of the decoders 2 occurs (it must be noted that at each moment in time, as many decoders 2 are selected as many units circulate in block 4 ) and, accordingly, the frequency of occurrence of the unit at each output of any of the decoders changes accordingly. The purpose of the code weight assignment unit 8 (FIG. 3) is to make changes during operation (i.e., without generator) the number of units circulating in block 4. For this, block 8, in accordance with the incoming signal, which indicates an increase or decrease by a certain number of units in block 4, blocks the feedback circuit of block 4 at events at the output of 7 units — in the case of a decrease in the number of units; In addition, the initial code can be sequentially recorded using block 8 in block 4. The code weight setting block contains elements AND 19-21 and the element OR 22. The device operates as follows. In the controlled shift register 4 bus 9 through the block assigning the weight of the codes 8 receives the tuning code with the specified weight k. At the same time, block 4 adjusts to issue permitting signals for K from 1 arbitrary output buses. The number of KMO can be changed from 0 to 1 depending on the weight of the setup code. Since the signals coming from the outputs of block 1, which is a sensor of pseudo-random evenly distributed numbers, to the inputs of block 4 are of a pseudo-random nature, the change of code combinations with a given weight K in block 4 also occurs randomly and, accordingly, the selection of K from 1 decoders 2 random. The operation of block 4 is as follows. If in this tact on. 1 is the output of block 1 connected to the inputs of block 4, the signals are zero, then block 4 in this clock cycle operates as a normal shift register. If the input random vector formed on 1 outputs of block 1 has single components in some bits, then the corresponding bits of block 4 are open; Switched on both their inputs and outputs, and information signals moving between the bits of block 4 bypass the disabled bits of block 4. Thus, in each step of the shift, the bits of the code recorded in the controlled register 4 are jumped over the bits register, marked by units in the input vector formed by block 1. The probability of occurrence of a permit signal at input 3 of each of the decoders 2 is determined by the probability of occurrence of a unit in the corresponding bit of block 4 and is equal to. Each of the allowed decoders 2 at a given time generates a single signal at one of its outputs, the number of which is determined by a random t-times by a random combination on the corresponding group of outputs of block 1. Therefore, at each input, single signals are received at the inputs of randomly selected K flip-flops 5 . It is these K selected triggers 5 that change their state to the opposite, while the remaining triggers 5 retain their previous state. This functionality of the triggers 5 is due to the fact that they operate in counting mode. Thus, a change in state is achieved (switching the signal on a given number of outputs. The generator is controllable. It is possible to set the probability of a signal change on each output in accordance with the formula where K} 0.1, ..., lj In the private In the case when K 1, we obtain in each clock cycle a change in the state of only one generator output. The sequence of such pseudo-random codes, having received in literature the name of the sequence of pseudocyclic codes, finds in practice the testing of digital circuits Compared with the prototype, the proposed generator has additional capabilities that improve its properties as a source of pseudo-random test signals designed to control digital circuits, in particular, the ability to generate pseudocyclic codes characterized by a level difference of the signal on only one output at any moment time is especially useful if, when applying independent random signals to the inputs of the circuit under test, conditions arise for a time indefinite STI or race fronts. In this sense, the proposed generator has virtually no restrictions in use. Pseudocyclic codes can be used when checking any combinational or logic circuits with memory — usually in systems with a common information channel for fetching device addresses, control decoders, or strobe-. data transmission system schemes. In addition, the proposed generator allows for a higher rate of generation of pseudo-random codes in comparison with the prototype. Compare the rate of generation of the proposed generator and prototype. The generation rate is determined by the frequency of the clock signals that synchronize the operation of the generator blocks. However, this parameter cannot be selected arbitrarily. In order for the timing relationships necessary for proper operation of the generator, the maximum delay for the propagation of the signal along the longest path in each of the blocks must be equal to wax where is the period of the clock signals; tn is the switch delay time. no trigger. Judging by the structure of the blocks of both the proposed generator and the prototype, the longest delay takes place; for block 4. If r is the length (number of elements) of a chain of consecutively connected logical elements AND and OR, which the signal must pass without distortion, and Cjcp is the average signal delay time for logic elements, determined from the passport data for the series of logic elements used, then it must be fulfilled. If it is assumed that the proposed and known getzers have the same number of output channels N, then 2 s for the prototype and the proposed generator are defined respectively as follows 2N N 7, wherein 2 - the number of outputs of decoders used. If we neglect the value of t, then the following reasoning implies that the speed of the proposed generator is higher by cp-t. Cf-l times, i.e. the generation rate for the proposed generator can be increased in comparison with the prototype by as many times as the outputs each of the depesffrators are introduced into the scheme of the proposed generator. Formula of the Invention A pseudo-random code generator containing a M-sequence generator, the first group of outputs which is connected to a group of inputs of a controlled shift register, the control of which in turn is connected to the output of a block for setting the weight of a code, the first input of which is the control input of the generator the clock input of which is connected to the clock inputs of the generator M-g of the sequence and the controlled shift register, the output of which is connected to the second input of the code weight setting unit, characterized in that generator speed, it contains n groups of triggers and n, decoders, the control inputs of which are connected to the output group of the controlled shift register, respectively, the outputs of the second, third, ..., 1st () generator groups of the M-sequence are connected to the corresponding inputs the first, second, ..., n-th decoders, the outputs of each i-ro (, 2, ..., p) of the decoder are connected to the counting inputs of the corresponding i-group triggers, the outputs of which form the i-th group of generator outputs . Sources of information taken into account in the examination 1. Authors svititelstvo USSR 436340 ,. kl.Ab F 1/02, 1973. 2. USSR author's certificate 440777, class C. About F 1/02, 1973. 3. USSR author's certificate No. 696510, class C. 06 F 1/02, 1977 (prototype) . .

Claims (1)

Claim A pseudo-random code generator containing an M-sequence generator, the first group of · outputs of which is connected to a group of inputs of a controlled shift register, the control input of which is connected to the output of the code weight setting unit, the first input of which is the control input of the generator, the clock input of which is connected to the clock the inputs of the M-sequence generator and a controlled shift register, the output of which is connected to the second input of the code weight setting unit, characterized in that, in order to increase the speed of the generator ora, it contains η trigger groups and η decryptors whose control inputs are connected to the group of outputs of the controlled shift register, respectively, the outputs of the second, third, ..., 1st (1 = n + 1) groups of the M-sequence generator are connected to the corresponding inputs of the first, second, ..., ηth decoders, the outputs of each i-ro (i = 1,2, ..., n) of the decoder are connected to the counting inputs of the corresponding triggers of the i-th group, the outputs of which form i- th group of generator outputs.