SU640344A1 - Pseudorandom pulse train generator - Google Patents

Description

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The invention relates to the field of computer technology and can be used to solve a wide class of problems by statistical modeling, as well as as a generator of test sequences in automatic monitoring and diagnostic systems using various probabilistic methods for detecting failures in digital circuits.

A pseudo-random pulse generator is known, comprising a p-bit shift register, a clock pulse generator, modulo-two t-adders, and a switch comprising n groups of switches in t-rows.

The disadvantages of the known are in great complexity as well as the impossibility of changing the probabilities of the signals at the outputs.

A pseudo-random pulse sequence generator is also known, which contains a main register with a modulo-two adder in feedback circuit 2.

The disadvantage of the known generator is the inability to change the probabilities of the signals at its outputs.

The aim of the invention is to enhance the functionality of a pseudo-random pulse train generator by altering the probabilities of the signals at the generator outputs.

The generator of pseudo-random pulse sequences contains the first and second blocks of the AND elements, the first and second blocks of triggers, the first and second elements of OR, the additional register and the register of the mask, according to the number of bits of which the nerve and the second elements of AND and

the OR element, the output of each of which is connected to the first input of the second element AND the corresponding bit and to the trigger input of the subsequent bit of the main register, and the inputs of the OR element

through the first and second elements AND of the corresponding bit connected to the outputs of the trigger of the same bit of the mask register and the main register, respectively, the input of the main register is connected to the output of the second element OR, whose inputs are connected to the outputs of the second block of elements AND whose inputs are connected to the outputs of the second block triggers and to the second group of outputs additional

register, respectively, the first input of the second block of elements And is connected to the output of the first element —OR, whose inputs are connected to the outputs of the first block of elements And, whose inputs are connected

to the outputs of the first block of flip-flops and to the first group of outputs of the additional register, respectively, whose input is connected to the output of the modulo-two adder.

The drawing shows a functional diagram of the proposed generator.

The generator of pseudo-random pulse sequences contains a n-bit main register 1 with adder 2 modulo two in the feedback circuit, consisting of clocked counting triggers 3 (T-V-type triggers); block of 4 elements And 5; block 6 elements And 7; block 8 triggers 9; block 10 triggers 11; elements OR 12 and OR 13; additional register 14, divided into / -digit groups 15 and containing one (last) group of / -1 triggers 16; mask register 17, to the outputs of which bits are connected elements AND 18 and AND 19, associated with elements OR 20, the output of each PZ of which is connected to the first input of element AND 19 of the corresponding bit and to the input of trigger 3 of the subsequent bit of the main register 1, and the inputs of the element OR 20 through the elements 18 and 11 of the corresponding bit are connected to the outputs of the flip-flops 21 of the same bit of the register of the mask 17 and to the outputs of the flip-flops 3 of the main register 1, respectively. The input of the main register 1 is connected to the output of the element OR 13, the inputs of which are connected to the outputs of block 6 of elements 7. 7. The inputs of block 6 are connected to the group of outputs 22 of the additional register 14 and to the outputs of block 10 of flip-flops 11, respectively, and the zero output of trigger 11.1 is connected the input element AND 7.1 is block 6, and the unit output of this trigger is connected with the input element AND 7.2, the zero output of trigger 11.2 is connected with the input element And 7.2, and the unit output of this trigger with the input element And 7.3, etc. Input 23 block 6 is connected to the input of the element OR 12, which inputs connected to the outputs of block 4. The inputs of block 4 are connected to the group of outputs 24 of the auxiliary register 14 and to the outputs of block 8 of flip-flops 9, respectively, the zero output of flip-flop 9.1 is connected to the input of the element 5.1 of block 4, and the single output of this flip-flop is connected the input element And 5.2, the zero output of the trigger 9.2 is connected with the input of the element And 5.2, and the single output of this trigger with the input of the element And 5.3, etc. The input of the additional register 14 is connected to the output of the adder 2 modulo two. Each group 15 of the additional register consists of triggers 25 (T-V-type), the outputs of each of which are associated with the counting input of the trigger 25 of the next bit.

Tires 26 are set to the inputs of the flip-flops 21, the mask code is set, inputs of the triggers 9 and I are set to tires 27, settings of 1groups 15 and triggers 16 of the additional register 14. A sync drive 28 is triggered for all synchronous inputs of triggers 3, 25 and 16.

The proposed generator of pseudo-random sequences works as follows.

At the initial moment of time, any l-bit number other than zero is written to the main register 1 (from the computer or from the keyboard of the console). The register of the mask 17, intended to fix those bits of the register 1, which will continue to store the previously recorded states "1 or" O, i.e., will be passive, an additional register 14, intended to supplement the number of active triggers of register 1 to bits (while maintaining the condition for generating a maximum period sequence), triggers 9 of block 8, and triggers 11 of block 10, intended for setting up groups 15 and triggers 16 of additional register 14. In the event that all bits of register 1 are supposed to remain active, all triggers 21 of register 17 on buses 26 will be scored "units, and in all triggers 9 of block 8 and AND block 10 on buses 27 will be scored" zeros. At this setting of the device, the signal from the single output of trigger 3 in any discharge goes through element 18, the second input of which receives potential 1 from the single input of trigger 21, and through element OR 20 enters the counting input (V - inputs) of trigger 3 the next bit in the register number of the register 1. The signal 19 does not pass through the AND 19 element of this bit, since the element 19 is closed by the potential “O from the zero output of the trigger 21 of the same bit”. At the moment the clock signal arrives on the bus 28 to the snoods (T-inputs) of all the triggers 3, each trigger 3 is set to the "new state," which is the sum modulo two "old state of this trigger 3 and" old The state of trigger 3 is the previous one by the digit number.

Installing the next state of the trigger 3 of the nerve discharge of register 1 differs from the installation of the other triggers 3. Since the "new state of the first register bit 1 is obtained as a result of modulo two" of the old state of the trigger 3 of this bit and the the state of the last (n-th) bit, to the counting input of trigger 3 in the first bit, it is necessary to send a signal from the output of adder 2. The signal from the output of adder 2 passes through AND 5.1, OR 12, AND 7.1, OR 13 elements (elements N ° 5.1 and and 7.1 open potential "1 with bullet exits

flip-flops 9.1 11.1, respectively) and enters the counting input of trigger 3 in the first discharge of register 1.

Let it be necessary to make the i-th generator bit passive and keep it permanently in a fixed state "1 or" O. "1 or" O is entered into trigger 3 of the i-ro bit of register 1, and the corresponding i-th bit of register of mask 17 is entered with "O. At this, the signal from the single output of the trigger 3 (i-1) -th bit passes through the elements AND la to OR 20 of this bit and is fed to one of the V-BXOs of the trigger 3 i-ro bit. Since the second pair of V-inputs of trigger 3 i-ro bits from a single output of trigger 21 of the same bit of the mask register G / is applied to the potential "O, trigger 3 does not change its state and becomes passive, and the signal under consideration passes through the element And 19, the open potential "1 from the zero output of the trigger 21 and then through the element OR 20 enters the counting input of the trigger 3 in (i + l) -OM discharge de. Thus, the i-th generator cell is bypassed during operation, and in the i-th cell itself, "1 or" O is pre-recorded there.

If in register 1 some triggers 3 are transferred to the passive mode, you need to connect to the register output 1 chain of the same number of triggers of the additional register 14 (the total number of triggers of the register covered by the feedback must be equal to l), trigger 3 in the last digit of the register 1 is always active. For this, the corresponding triggers 9 of block 8 and AND of block 10 are set to 1. For example, if trigger 1 is set to 1, then a chain of triggers 25 in the first group 15 will be connected to the main register 1. In this case, the signal with the output of the adder 2 passes through the triggers 25 of the first group 15 and enters the input of the element And 5.2, which is open, because the potentials 1 1 from the single output of trigger 9.1 and zero output of trigger 9.2 arrive at its second and third inputs. From the output of the And 5.2 element, the signal under consideration passes through the elements 12, 7.1 and 13 to the counting input of trigger 3 in the first register de register 1. If triggers 9.1 and 9.2 are installed in "1", then element 5.3 opens, connected with the output of the second group 15 and in this case, the chain of triggers 25 constituting the first and second groups 15 will be connected to register 1.

Finally, if all the triggers 9 of block 8 are set to "1, AND 24 will open and all groups 15 of register 14 will be connected.

If it is necessary to connect a chain whose number of triggers is not a multiple of the number of triggers in the group, triggers 16 are additionally used, each of which is controlled by the triggers 11 of block 10. The triggers 16 are connected according to the same principle as the groups 9.

In order not to distort the signal when passing it through the schemes I and III., In case of need to bypass a large number of located passive bits, the main register 1 mol. Will be divided into groups and instead of bypass individual passive bits the whole group consisting only of passive bits.

Traversal of groups is carried out according to the same principle as on traversing individual bits. The proposed generator has the possibility of rearrangement, due to which pseudo-random signals can be obtained at randomly selected bits of the main register of the generator. Using this property, it is possible to realize a generator with a different number of bits n chosen from a number of numbers, 3, 4, b, 7, 15,

22, 60, 63, 127, ..., without changing the structure of the generator. This ensures the maximum length of the period of the sequence for the corresponding values of p.

The proposed generator has the ability to vary the probabilities of the signals at the outputs of the generator (for any given outputs, signals with a mathematical index of O, 5, O, or 1 can be given). When using the proposed

The generator as a generator of pseudo-random test sequences in devices for controlling digital circuits, the property of changing the probabilities of signals, shortens the test time and in many cases eliminates the supply of combinations of input signals causing critical races.

Claims (2)

1. USSR Author's Certificate No. 375769, cl. G 06 F 1/02, 197. 2. USSR author's certificate number 468231, cl. G 06 F 1/02, 1973. 1 g