SU890391A1 - Pseudorandom number generator - Google Patents

Description

The invention relates to computing technology and can be used as a device for obtaining random numbers in solving problems by the Monte Carlo method, for constructing random process generators with specified characteristics, as well as for generating random processes with a uniform spectrum used to identify automatic control systems. . Known pseudo-random number generator, containing two shift registers and a group of adders modulo two 1). The disadvantage of this generator is the complexity of the structure, the method of synthesizing such a pseudo-random number generator is much more difficult. In addition, to construct a pseudo-random number generator, it is necessary to choose such structures of the original generators, for which the periods are mutually prime numbers. Also known is a parallel pseudo-random number generator, which is distinguished by a maximum speed value and allows the formation of multi-digit pseudo-random numbers {2. The disadvantage of this generator lies in the complexity of the formation of shifted sequences, determined by the number of inputs of modulo-two adders. Each adder has an average of t / 2 inputs. At the same time, the cost of equipment required for the schemes of the formation of shifted sequences is several times higher than the costs incurred in building the ring shift register. The closest technical solution to the present invention is a pseudo-random number generator containing a t-bit shift register, two AND elements and an OR element, which implement the addition operation modulo two t-th and j-ro contents

bit register shift. The j-ro bit number, depending on the width of the shift register m, is selected from the UZ table.

The disadvantage of this device is the difference in the probability of the occurrence of zero or one at its output from

0.5

The purpose of the invention is to improve the accuracy of the generator.

The post-HELD goal is achieved by the fact that, in the pseudo-random number generator, which contains the t-bit shift register, ga, the first element I, to the first input of which is connected the inverse

output of the n-th bit of the shift register RC, the second element AND, to the first input of which the direct output of the n-th bit of the p shift is connected, the element OR, the output of which is connected to the input of the first bit of the shift register, additionally introduced the third element AND , the fourth element is AND and the element is OR NOT, and co. the second inputs of the first and second elements AND are connected to the inverse and direct outputs of the j-ro bits of the shift register, respectively, and the outputs of the first and second elements AND are connected to the first and second inputs of the OR-NOT element, to the inputs of the fourth element AND are connected to the inverse outputs t -1 of the first bits of the shift register, and the output of the fourth element AND is connected to the third input of the element OR NOT and to the first input of the third element AND, to the second input of which is connected the inverse output of the n-th digit of the shift register, the output of the element, OR -NOT connect .k first input of the OR gate, the second input of which is connected to the output of the third element I. In FIG. 1 shows a functional diagram of the generator; in fig. 2 - the sequence of states of the known (a) and proposed (b) generators with m 3 and j 1. The generator consists of a register of shift 1, first, second and third elements AND 2, 3, fourth element AND 5 of element OR NOT 6, and the element OR 7- To the first input of the first element I 2 there is an inverse output of the t-th digit of the shift register 1, to the first input of the second element I 3 the direct output of the n-th bit of the shift register 1 is connected, and the output of the OR element 7 is connected to the input of the first bit of the shift register 1. To the second inputs of the first and second element I 2

and 3 are connected to the inverse and direct outputs of the j-ro bit of shift register 1, respectively, and the outputs of the first and second elements AND 2 and 3 are connected to the first and second inputs of the OR-NOT 6 element, and the inverse outputs t are connected to the inputs of the fourth And 5 element -1 of the first bits of the shift register 1 and its output is connected to the third input of the element OR NOT 6 and the first input of the third element AND, to the second input of which the inverse output of the n-th digit of the shift register 1 is connected, the output of the element OR NOT 6 is connected to the first input of the element OR 7i and to the second input of the el ment OR 7 connected to the output of the third AND gate 4.

The generator works as follows

In the initial state, the shift register contents of the k-ro bit can take the value zero or one. Unlike the known generators in this generator at the initial moment in the bits of the register 1 there can be a zero code. Depending on the initial code at the output of the combinational part, i.e. at the output of the element OR 7, a symbol is generated, zero or one. Upon arrival of the clock pulse, the contents of shift register 1 are shifted one bit to the right, and the first digit is written to the character generated at the output of the element OR 7. With the contents of the first t-1 bit of shift register 1, other than zero, elements 2 , 3, 6, and 7 implement the modulo operation of modifying the two contents of the j-ro and the t-th bits of the shift registers. In this case, the M-sequence is generated, as in the well-known. Further, when the first co-1 bits of the register 1 are zeroed, the zero co-combination at the output of element 5 appears to be a single level, which provides the appearance at the input of the first bit of shift register 1 zero. When the next clock pulse arrives, the shift register 1 contains zero values in all bits. The zero occurrence in the m-th bit ensures the appearance of a unit at the output of the element, which through element 7 enters the input of the first bit of the shift register 1. The next clock pulse provides the appearance in the shift register 1 of the combination 100 ... O, t. e. zeros in all bits except

Claims (3)

Claim A pseudo-random number generator containing an m-bit shift register, 33 first element,, to the first input of which is connected the inverse output of the t-th category of the shift register, the second element And, to the first input of which is connected the direct output of the m-th category of the shift register, element OR, the output of which is connected to the input of the first bit of the shift register, characterized in that, in order to increase the accuracy of the generator, it contains the third element AND, the fourth element AND, the element OR-HE, and the inverters are connected to the second inputs of the first and second elements AND the clear and direct outputs of the j-ro discharge of the shift register, respectively, and the outputs of the first and second elements AND are connected to the first and second inputs of the OR-HE element, the inverse outputs of t-1 of the first bits of the shift register are connected to the inputs of the fourth element AND the fourth AND element is connected to the third input of the OR-HE element and to the first input of the third AND element, to the second input of which the inverse output of the mth digit of the shift register is connected, and the output of the OR-HE element is connected to the first input of the OR element, to the second input whose connection The output of the third element I. 30 Sources of information taken into account in the examination 1. Yakovlev V.V., Fedorov R.F. Probabilistic computers. L., Mechanical Engineering 1974, p. 263 2. Ibid., P. 254. 3. In the same place, with. 247 (prototype). '111 011 101 οίο 001 100 110 111 011 101 010 001 Ltd 100 110 Φοί.2 VNIIIPI Order11007 / 78 Circulation 748 Subscription Branch of PPPPatent, Uzhhorod, st. Project, 4