SU1141379A2 - Test specification device - Google Patents

Abstract

DEVICE FOR ASSIGNING TESTS on author YEV, No. 1038926, characterized in that, in order to increase the reliability of control and deployment of the device, a mode switch and an address switch containing the groups of second, third and fourth elements AND NOT, the element NOT connected by input to the first inputs are introduced into it the second elements NAND, and the output to the first inputs of the third NAND elements connected by the second inputs with the corresponding second outputs of the address setting block, the third inputs with the corresponding discharge outputs of the pulse counter, and the output Amy - with the first input. Four of the fourth NAND elements connected by second inputs to the outputs of the second NAND elements connected by the second inputs to the corresponding outputs of the number register, and the first inputs through the mode switch - with buses Logical O and Logic 1, and the outputs of even NI elements are addressable device outputs.

Description

one

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The invention relates to general purpose control and control systems and can be used to test, monitor and diagnose faults, binary I / O devices, presented in the form of code combinations. According to the main author No. 1038926 a device is known that contains an AND block, an initial code setting block, a first input connected to the output of the first driver and the first inputs of an AND block, the second inputs of which are connected to the outputs of the initial code setting block, and a serially connected pulse generator, a pulse counter, the decoder and the second pulse shaper, the output of which is connected to the R input of the pulse counter, the input of the first pulse shaper and the input of the pulse generator, as well as the control unit, the summation unit , -pigy of the number, additional element I, address setting block and switch, outputs through a number register connected to the device outputs with the first inputs of the switch and the block of adders, the second inputs of which are connected to the outputs of the initial code setting block, the second input block connected to the input of the second pulse generator and with the first output of the control unit, the second output of which is connected to the second input of the switch, the third inputs of the switch are connected to the first outputs of the block of adders, Rd-d output of which is transferred to Connected to the PJQ transfer input of the adder unit, the third output of the control unit is connected to the first input of the additional element AND, the second input connected to the output of the pulse generator, the output to the C input of the number register, the second inputs of which are connected The address of the output is connected to the S-inputs of a pulse counter, in which the initial code setting block contains an AND element, a switch, an installation register and a series-connected delay element, an NAND element and a shift register, and outputs connected to the outputs of the block, the first input of the element I is connected to the input of the block, the second input is with a switch, and the output is with the C input of the shift register, C. the input of which is connected to the output of the delay element, Yy, the input to output D of inputs - with the outputs of the adjusting register, the first inputs connected to the bus logical 1, and the second inputs - to the bus logical 0, the second input of the element IS NOT connected to the input of the unit, the first input of the switch connected to the bus logical 1, and the second input to the bus logical O. The device provides the formation of verification tests such as pseudo-random, shear, chess, permanent codes, as well as a test with an ordered structure of binary codes that change according to the +1 principle. These tests allow checking electronic units including units with multicast operative memory. In this device, the first digit of the address changes its state every time the memory is accessed. The second bit of the address changes its value after two cycles (two addresses), and the third bit changes its value, and so on. those. each next address bit is switched in two races less than the previous one. The last address bit of the address will change its state one time when going into the second half of the addresses of the RAM being scanned f13. However, checking the address part of the monitored block in different bits of the address bus occurs with different frequency of code change. At the same time, only the first bit is actively affected by codes with the maximum frequency of symbol change. Other bits of the address buses are not checked for maximum speed, which reduces the reliability of checking the electronic blocks with memory. This is especially true in semiconductor memory devices that contain address decoders inside the chip. In such memory devices, it is necessary to check the stable operation with the limiting (minimum) temporal ratios of the components of the cycle time along different address chains in order to check the reproducibility of dynamic parameters for identity

memory circuits by delay time in the address descrambler.

The aim of the invention is to increase the reliability of control and expand the field of application of the device by checking the maximum performance of each bit of address buses.

The goal is achieved by the fact that the device includes a mode switch and an address switch containing a group of second, third and fourth AND-NOT elements, an NO element connected by an input to the first inputs of the second AND-N elements and an output to the first inputs of the third AND elements. NOT connected by the second inputs to the corresponding second outputs of the address setting block, the third inputs to the corresponding bit outputs of the pulse counter, and the outputs to the first inputs of the fourth NAND elements connected by the second inputs to The outputs of the second NAND elements are connected with the second inputs to the corresponding W output of the number register, and the first inputs through the mode switch with buses Logical O and Logic 1, and the outputs of the fourth NAND elements are the address outputs of the device.

In the proposed device for setting tests, the target is reached by rutating binary codes through the newly entered address switch, the group of inputs of which receive the ordered codes from the outputs of the pulse counter, and the other group of inputs - codes from the output of the number register that together with the adder, the switch and a block for setting the initial code, a pseudo-random number generator, which is then set by the operator into the formation mode of ordered codes with a cyclic shift of the initial code of the test program we. In this case, when the operator in the switch turns on the address of the control key, the address will pass codes through the switch to the address outputs of the device, which will test each bit of the address of the block being checked at maximum speed. When the control key is switched off at the switch, the address codes will pass through the address switch through the switch of the pulse counter outputs to the address outputs.

A significant difference between the known device and the proposed one is the presence of the address switch in the latter, which allows the use of the pseudo-random number generator available in the known device to form an address polling program that ensures that all address bits are equally reliable in the entire information volume verifiable memory.

Devices are known that allow the dynamic characteristics of the address input circuits of storage devices to be checked by galloping tests. The principle of control of memory blocks by galloping tests is based on the organization of checking all possible address transitions. This is done by successively sampling each address after affecting all other addresses. In this case, the calls are made in the follow up sequence of the address change;

The 1st cycle is 0-0-1-0-2-0-3-0-4-0 ... 0 (N-1), where 0,1,2,3 .... address number;

2nd cycle 0-1-1-1-2-1-3-1-4 -... 1 (N-1);

3rd 1SCHL 0-2-1-2-2-2-3-2-2-2-2 ... 2 (N-1);

(Y-1) th cycle 0- (N-1) -1- (N-1) -2 (N-1) -3-;

) ... ... (NI) - (NI).

Such an organization provides j with all possible address transitions: and a certain dynamics of signal change in the VPO each address bus address. But at the same time, there is no verification of each bit of address buses for the maximum frequency of signal changes. This can be seen if you write code combinations that arrive at the address tires of the tested memory block.

1st cycle; Address No .: 0 0 ... 0 O O O

O 0 ... 0 O O, 1 0 ... 0 O 1

o 0 ... 0 o o o, .. o 1 o 0 ... 0 o o o o, 0 1 1 0 ... 1 o o 0 ... 0 o .. o o o 1 0 .. N-1 1 1, .. 1 1 (N-1) -and cycle Address number 0 ... 0 O1 ... 1 1 1 O ... O O 1 1 ... 1 1 1 0 ... 0 1 О 1 ... 1 1 1 0 ... 0 1 1 1 ... 1 1 1 1 ... 1 1 1 1 ... 1 1 1 From these code sequences it is clear that The signals in each bit of the address are provided, but the effect of the maximum frequency of changing the signal in each bit is provided only in certain sections of the address, which reduces the reliability of the address inputs of the semiconductors of the microcircuits. In addition, a full pack of all address transitions is performed in N control cycles, each of which contains N reference cycles. Therefore, a complete control of the memory device is carried out in N accesses. Microcircuits are known (for example, the MK 4164 (USA) with an information capacity of 64K words (). In this case, the full control of all address transitions by a galloping test is carried out in 2x (2) reads (where 2 - takes into account the write and read cycles). The invention provides verification of dynamic characteristics for each bit of address busses of the tested semiconductor memory devices for 2x20N hits (when 2x20x2 calls are required), which is much faster than a galloping test. The action of each bit address busses. In Fig. 1 shows a functional diagram of the device for setting tests; Fig. 2 is a schematic diagram of the initial code setting block; Fig. 3 is a schematic diagram of the control unit; Fig. 4 - time The diagram of the address switch. The device (Fig. 1) contains the address setting block 1, the counter 2 pulses, deprafrater 3, the second driver 4 pulses, the generator 5 clock pulses, the first driver 6 pulses, block 7 ass neither the initial code, the spzmmator block 8, the switch 9, the number register 10, the block 11 elements AND, the additional element 12, the control block 13, the address switch 14, the first output 15 of the control block, the output 16 of the first pulse generator, the outputs 17 of the initial block code, the second 18 and third 19 outputs of the control unit, the outputs 20 of the number register, the outputs 21 of the pulse counter, the second outputs 22 of the address setting unit, the address outputs 23 of the device. The initial code setting unit 7 contains a switch 24, an AND 25 element, a delay element 26, an AND-NOT element 27, a shift register 28, an installation register 29. / 1 Iiji (iK 13 yiT) (HH contains a second switch 30, the first and the second moving the contacts of which are connected, respectively, to the outputs 18 and 19 of the control unit 13 and connected to the buses Logic 1 or Logic O, as well as the Reset button 31 and the RS flip-flop 32. The address switch 14 contains the groups of the second 33, third 34 and fourth 35 elements NAND, switch 36 modes and the element is NOT 37, Block 1 setting the address of the It is a toggle register, each time a series of which is made on a double toggle switch with a neutral position. The first and second contacts of each switch are interconnected and connected to the first group of outputs of the address setting block 1 and can be connected to the bus. Logic O Quarter contact of each A toggle switch is connected to the second group of outputs 22 of the address setting block 1 and can be connected to the bus. Logic О The address setting block 1 is needed to fix the outputs of the counter 2 pulses to the O or T position when localizing non-fault in the block under test, as well as to reduce the counter size depending on the information capacity of the test object. In the prototype in the address setting block 1, a sixteen-bit toggle register is used on the PT6-15B toggle switches, which ensure that each output of the pulse counter is installed in one of three positions: 1, O, Counting. Pulse counter 2 is designed to form a complete set of ordered symbols that stimulate input to the address buses of the monitored unit, as well as to obtain information about the cycle of the control program. A prototype pulse counter was used in the prototype. The decoder 3 serves to receive the start signal of the first driver of the 4 pulses when the maximum state of the counter of 2 pulses is reached. The shaper 4 pulses is required for setting the initial 10-digit register, the pulse counter 2, starting the second shaper 6 pulses, and preparing the generator 98 and rIyJt (: on to the river-Poteau and P (; cycle. Shapes 4 and 6 pulses are executed on standard NAND logic circuits. A clock pulse generator produces a pulse train for changing the state of the pulse counter 2 and the number register 10. The prototype used a pulse generator with an IS pulse circuit with a pulse period of 0.5. 2,4,10000 MKS. Formi The pulse generator 6 controls the operation of the initial code setting block 7 and the 11 element block I. The initial code setting block 7 generates the source code of the test program in the form of a twenty-bit binary number that changes its value after passing the full cycle control of the test block. Block 8 adders with ring transfer, the pseudo-random code type tests. A test sample was applied to a twenty-bit adder on 133IMZ microcircuits. The switch 9 of the number is designed to transmit the code of the number from the block 8 of adders of the pin i-ro output to the i + 1 input of the register 10 numbers. The switch switches from the control unit depending on the mode selected by the operator. The switch is complete on the 2I-OR-NOT logic circuits. Register 10 of the number serves to set the binary code coming from the switch 9 of the number. In the prototype, a twenty-bit number register on D-triggers with a counting input (133TM2 chips) was used. Block 11 of the AND elements is a buffer cascade in the impulse setting circuit in register 10 of the number of the source code arriving from block 7 of the initial code. The scheme And 12 prohibits the passage of counting pulses on the register 10 numbers. The prohibition signal is supplied from the control unit 13 in the test generation mode with a constant code. The control unit 13 is used to reset the number of the register 10, the pulse counter 2, the pulse generator 5, the start code block 7, and also to control the operation of the Islam switch 9 and the AND 13 circuit. Changing the MOB mode of operation, the operator performs buttons and switches you entered on the control panel. The address switch 14, depending on the position of the switch 36, passes the binary code from the outputs 2 of the counter 2 pulses or from the outputs 2 of the register 10 of the number to the address outputs 23 of the device. The device works in the following way. The initial state of the device units is determined by the position of the setting switches in the address setting unit 1, the switch 24 and the installation register 29 in the initial code setting unit 7, the switch 30 and the buttons 31 in the control unit 13, the switch 36 in the address switch 14. The position of the toggle switches in the address setting block 1 determines the number of bits working in the counting mode in the 2-pulse counter, depending on the information capacity of the tested multicast memory blocks. For example, when checking a block with an information capacity of 8K words (8192 words 2), the first thirteen toggle switches should be set to the neutral position, and the remaining toggle switches should be set to zero. In this case, the first thirteen bits 2 of the pulse counter will operate in the counting mode, and 14–16 bits are set to state 1, since the 14–16 S inputs of the pulse counter 2 receive zero potentials. The position of the switch 24 in block 7 of the initial code setting determines the operation mode of this block. When the switch 24 is turned on, the block 7 of the initial code setting works in the shift mode of the source code dialed by the operator on the setup (toggle) register 29, after a full search of the counter 2 pulses o When switching off the bodies 24, the block 7 will always have the initial code the outputs 1 are equal to the information collected on register 29, since the information shift will be prohibited on the element 25. 25. Consequently, the initial state of block 7 is determined selected, using the switch 24, the operation mode of the start 7 unit the code and the source code dialed on the register 29 10 The position of the switch 30 in the control unit 13 determines the operation mode of the device when generating tests such as constant code, shift code, pseudo-random code. In the position of the Post switch 30 at the outputs 20 of the register 0 of the number, the code will have the code value at the outputs 17 of the block 7 of the initial code. In the Shift position, the information switch 30 at the outputs 20 of the register 10 will shift by one bit relative to the code at the output 17 of the unit 7 setting the initial code at each device operation cycle (i.e., when the state of the counter of 2 pulses changes by - ((- 1 In the switch position 30, the information on the outputs 20 of the register of the number 10 will change according to a pseudo-random law depending on the code on the outputs 17 of the initial code setting block 7. The initial position of the switch 30 may be arbitrary to depends on the selected operator test mode. Button 31 in the control unit 13 in the initial state provides a trigger O for the trigger 32, and 1. for the R input, 1. At the outlet 15, the trigger 32 will be 1 When you press the button 31, the output 15 will O, providing the formation of the initial setting signal for the initial code set block 7 through the pulse shaper 4, which is the element I, the initial negative polarity setting signal is fed to the R input of the 10th register, setting it to the initial state (state O) . The position of the switch 36 in the switch 14 addresses provides the passage of binary codes from the counter 2 pulses or from the output of the register 10 numbers. Moreover, if the key 36 is set to the Pseudo position, then numbers from the register output 10 are allowed to pass through the address switch 14 to the device outputs 23, and if the switch 36 is turned off, the address switch 14 passes address codes from the pulse counter 2 outputs. The mode of operation of the address switch 14 is chosen arbitrarily by the operator, therefore, the initial position of the key 36 can be any.

The operation of block 7 of the initial code setting consists in the formation of the source code of the test program. The first source code is dialed by the operator on register 29. After pressing button 31 on the remote control of control unit 13, the code dialed on register 29 is rewritten into shift register 28 After searching all the values of the counter 2 pulses, the overflow signal from the output of the decoder 3 through the drivers 4 and 6 pulses and through the element 25 it enters the input C1 of the shift register 28 and shifts the originally recorded code by one bit. The new code is the initial (source) code of the next test program. For example, consider the operation of the initial code setting block, if the register 00 ... 01 is entered on register 29. By pressing the button 31 in the control block 13 from the output of the trigger 32 to the input 15 of the initial code setting block and to the second input. the first 4pulses generator (fig. t) receives a negative polarity reset signal, which: is delayed on the delay Element 26 and is fed to the C2 input of the shift register 28, at the input V2 of which a signal is generated from the IS-27 element of positive polarity the total duration of the signals, on the first and second inputs of the NAND element 27. On the negative edge of the signal at input C2, the code typed on the toggle switches of the register 29 will be written to the shift register 28, i.e. code 00 ... 01 will be recorded.

The positive potential at the input V2 permits the recording of information on the D-inputs of the number register and inhibits the shift, the zero potential prohibits the recording on the D-inputs and permits the shift. The output of Q1 will be 1 at the outputs of Q2.:.Q20 - O,

From the output of the pulse shaping device 6 to the input 10, pulses are received, {{1} worked on the falling edge of the reset signal from the output 15 of control unit 13 or the overflow signal of the counter 2 pulses. Shift clock pulses are fed to the C4f input of the register 28 through the AND 25 element. The first pulse does not shift the information.

as the input signal V2 still holds a positive signal. After a full cycle of control, i.e. reaching the maximum value of the counter 2 pulses, the second pulse will be sent to the input C1, the code of the number will be shifted to the second position of the shift register 2 The complete control cycle of the test block will be repeated with the new initial code.

Since the shift register contains 20 bits, after passing through twenty control cycles, the operation of the initial code setting block will repeat, i.e. again 1 will be recorded in the first digit of the shift register, but the reset signal at input 15 will not be, if the operator does not press the reset button 31 on the control unit 13. If necessary, you can disable the shift information toggle switch 24. In this case, at the input C1 of the shift register 28 will be O. At the same time, at the outputs Q1 ... Q20 of the shift register 28 after pressing the button 31 in the control unit 13 there will be a constant number code equal to. the value of the code dialed by the operator on the register 29. In the experimental device was applied twenty bit shift register on the IC 133I1.

In the control unit 13 in the Shift position, the first moving contact of the switch 30 to the control input of the switch 9 comes from the output 19 of the control unit 13, the signal O, allowing the code of the number to pass from the i-ro register output 10 to the input i + l-ro register 10 numbers, ensuring the formation of the Shift-type test, from the second moving contact of the switch 30 comes from the output 18 of the control block 13 times: the decisive signal Log. 1 to the second input element And 12.

In the position of the post output 18 of the control unit 13. To the second input of the element 12, a signal O is given, prohibiting the passage of clock pulses from the generator 5 pulses to the C input of the register 10 of the number. At the same time, the code recorded from the S-inputs of the register 10 of the number remains unchanged during the entire control cycle of the test block.

The button 31 forms a reset signal, the trigger 32 liqv rn g hrkkt

contact bounce when the operator 31 pushes and releases the button. From the output of the trigger 32 from the control unit 13, a reset signal is sent to the second input of the first driver 4 pulses and to the first input 15 of the starting code setting unit 7.

The proposed device provides for the formation of tests such as a pseudo-random code, a shift code, a permanent code, an ordered address code, and a newly added additional type - a pseudo-random address code. These tests allow testing, monitoring and diagnostics of electronic equipment, including blocks with a multicast semiconductor memory.

The formation of the test type pseudo-random code.

In block 13 of the control switch 30

Operator Installs on by Perm. In this case, with the blogging

The control signal enters the control input of the switch 9, allowing the passage of the number from the output of the block 8 of adders to the D-vbdy register of the 10th number, and simultaneously from the control block 13 the enable signals to the first input ele1 are received. And 12. Dp of bringing the device to the initial state in the control unit 13 by pressing the button 31, a negative polarity reset signal is generated, which passes through the second driver 4 and pulses and sets the counter of 2 pulses, register 10, generator 5 to the initial state. the pulses, in addition, the negative polarity reset signal from the output 15 of the control unit 13 is supplied to the initial state of the initial setting unit 7, in which the operator pre-dials the initial code using the register 29. The source code from output 17 of block 7 of setting the initial code through block 11 of elements And is written into register 10 of number, forming a binary code which is the first test information stimulus of a pseudo-random test, then the clock pulses from the generator of 5 pulses arrive at the counting input of the counter 2 pulses and through the element 12 - on the counting input of the register 10 numbers.

The initial number from block 7 of the initial code is fed to the first A inputs of the block 8 adders, the second B inputs of which receive the binary code from the output of the number register.

In block 8 of adders, the initial number is added to the code recorded in the 10-digit register from block 7 of the initial code. For example, the number 00011001 entered from block 7 of the initial code setting, entered by the operator on the tztbler register 29 in block 7 of the initial code set (for example, eight-bit words), which is the first test stimulus. The second test stimulus will be the result of adding

00011001 +

00011001

00110010

from the output of block 8 adders, the binary code is transmitted through the switch to the D inputs of the 10th register and when the first clock pulse arrives from And 12, it is written to it. Thus, the formation of the second information stimulus ends, which from the outputs 20 of the register 10 of the number is sent to the block under test and to the second B-inputs of the block 8 of adders, where the resulting code is added together with the source code

T 6

00110010 +

00011001 01001011

Upon receipt of the number of clock pulses at the counting input of the register 10, the summation result writes down the number 10 through the switch 9 to the register, forming the third test stimulus of the tests. Similarly, the fourth test is received.

01001011 +

oooligoi oTTooioo

To analyze the tests we write them in the following order.

00011001

00110010

01001011

01100100 The tests presented do not have an ordered structure, but are strictly deterministic in time, i.e. can be repeated in the same sequence, which is necessary when monitoring blocks of storage devices, when information is recorded in the first test cycle, and the next one is read. Such tests are called pseudo-random. In total, the proposed device can be formed in one complete test control cycle, where M is the information capacity of the test block, 2.3 ... 16 is the counter width of 2 pulses. Simultaneously with the formation of test tests on the monitored block, from the outputs 23 of the switch 14, address codes (address stimuli) are sent, according to which verification tests are recorded in the block under test. Moreover, if the switch 36 in the address switch 14 is disabled, then the zero potential from the switch 36 is supplied to the first inputs of the second AND-HAND 33 elements, all outputs of which will have unit potentials coming at the second inputs of the fourth AND-HRE elements 35 Therefore In this case, the ordered address codes from the outputs 21 of the counter 2 pulses will pass through the elements of the NAND 35 in this case. The ordered address codes are generated as follows. In the address setting block 1, the operator sets the required width of the 2-pulse counter. From the control unit 13 through the first generator 4 pulses, a signal is sent to the zeroing input of the counter 2 pulses to set it to the zero state. The code of the first address stimulus at the outputs 21 of the counter 2 pulses is 00 ... 00. This code is a pass. It goes through the address switch 14 to the outputs 23 and is directed to the address buses of the block under test. At this address, the first test code entered at the information inputs of the tested block from the outputs 20 of the 10th register is recorded in the checked block. With the arrival of the first clock pulse on the counting input, the pulse counter 2 changes its state according to the +1 principle, forming the code of the address stimulus sprinkled through the switch 14 onto the address outputs 23 of the device. At this address, the second block of information from the 20th register of the 10th number enters the block under test. When the maximum state of the counter of 2 pulses is reached, the signal from the output of the decoder 3 starts the first driver of 4 pulses, from the output of which the signal sets the register 10 and the counter of 2 pulses to the zero state and prepares the generator of 5 pulses for operation in the next cycle. On the falling edge of the signal of the first imaging device 4 pulses, the imaging unit 6 pulses, which controls the operation of the initial code setting unit 7 and the AND 11 element unit. Thus, from the outputs 23 of the counter 2 pulses, the binary code 00000000 00000001 000 is sent to the test unit. ..... 0010 0000011 000 0100 These tests have an ordered structure and determine the order in which the address is selected, at which the verification test is performed from the outputs of register 20 of the 10th number. The newly introduced address switch 14 allows the selection of the addresses of the checked memory block not only according to an ordered law, but also pseudo-randomly. To do this, you need to set the key 36 of the switch 14 of the address to Pseudo. In this case, from the output of the element NOT 37 to the first inputs of the third elements AND-NOT 34 (in the address switch 14) the potential of zero will flow. Therefore, at the first inputs of the AND-35 elements there will be unit potentials permitting the passage of pseudo-random codes from the outputs 20 of the register 0 to the number through the open elements AND-HE 33 and 35 to the address outputs 23 of the device. This allows you to check the stability of the recording, storage and reading of information in controlled memory blocks in an arbitrary order of address selection, which ensures the maximum approximation to the actual conditions of operation of memory blocks in digital computing systems. The test formation mode is a type of shift code and varieties of a chess code. In the control unit 13, the operator sets the switch 30 to the Shift position. In this mode, control block 13 receives a signal to the control input of the switch 9. In this case, the register 10 inputs are disconnected from the outputs of the adder 8 and connected through the switch 9 to their outputs, the output of the 1st digit of the register 10 connected to the D-inputs of the i + 1-th digit, the output of the last digit of the register of the 10th number is connected to the D-input of the first digit, forming a ring shift register. The source code of the number from block 7 of the initial code set by the pulse of the second driver 6 through the block 1 of the elements AND is recorded via the S input into the register 10 of the number. The recorded code is the first informational stimulus that is sent from the outputs 20 of the register 10 on the number to the test block, to the cell corresponding to the incoming address stimulus from the output 23 of the counter 2 pulses. With the arrival of the first clock pulse at the counting input of the 10th register, the code written into it shifts by one step, forming the next informational stimulus. When installed in block 7, the alternating code 101010 ... 10 at the output of register 10, the numbers will form with the type codes a chess test, which may be of the type 1100 1100 ... 1100 and others. Mode of formation of the test type constant code. The switch 30 in the control unit 13 should be set to the pos. In this mode, the control unit 13 receives a signal from the AND 12 element, which prohibits the passage of clock pulses to the counting input of the register 10 of the number. Therefore, in register 10, there will be a constant information recorded on the S-inputs from block 7 of the initial code setting through block 1t of elements I. To change the code in register 10, it is necessary to register a new code in block 7 of the initial code setting, then, when the button 3 is pressed in the control unit 13, a reset signal is generated, which is fed through the first driver 4 of the pulses to the obnu входt вход input of the register 10 of the number and the counter 2, and also prepares the generator 5 for operation. At input 15, a reset signal records the source code in block 7 of the initial code setting, from the output of which a new code goes to the inputs of an AND 11 block and with the arrival of a signal from the output of the pulse generator 6 pulses to the control input of the And 11 block of blocks, the code is written over S- inputs in the register of the number 10 and sent to the block under test. Further, in the process of monitoring the test block, the code from the output of register 10 of the number does not change. The test mode for maximum performance (maximum switching frequency) of each bit of the address bus of the test block is performed using a pseudo-random test. To do this, the switch 36 in the address switch 14 must be set to the Pseudo position, in the control unit 13, the switch 30 is set to the Position; enable key 24 and set code 00 ... 01 on the setup register 29 in block 7 of the initial code setting. When the start button is pressed in the control unit 13, the reset signal comes from the output 15 of the control unit 13 through the first driver of 4 pulses and twists the counter of 2 pulses, the generator of 5 clock pulses, the 10-digit register, block 7 of the initial code, the binary code being rewritten into the shift register 28 of the block 7 of the initial code setting and through the block of elements And 11 is rewritten into the register of the 10th number. Code 00 ... 01 is the first test stimulus, which from the outputs 20 of the register 10 of the number goes to the information inputs of the test block and the first group of inputs of the switch 14 is the address through which the code goes to the address outputs 23 of the device. Therefore, in this mode, the address code and the code of the recorded information will be the same. With the arrival of the first clock and pulse from the generator 5 code through the element 12 to the counting C input of the register 10, the interaction of the block 8 of adders, the switch 9 of the number and the register of the 10 number will result in the formation of the second checking stimulus, which will have 20. .. 17, 16 ... 4321 About ... About 0 .... 0001 1) + About .. About About ... 0001. ooTo This code will go to informational 20 and address 23 outputs of the system, and other test stimuli (codes) 20 ... 17, 16 ... 4321 O ... O O ... 0001 f O.,. About About ... 0010 5) About ... About About ... 0101 «« N) About ... About 1 ... 1111 The table shows the codes in order to follow them. Tact no. Units Address 20 ... 17 16 ... 43Z1 I.and, „-G -Lnfl-ll T o ... o o ... 0001 1 O ... OO ... 00102 O .. .O ... UN3 O ... OO ... 01004 O ... OO ... 01015 1111 N From the analysis of the results obtained in the first cycle (the cycle refers to the time for complete enumeration of all states of the counter bits of a pulse of 2 pulses) codes, you can see that they have an ordered structure that will provide an appropriate selection of addresses. At the same time, for the first bit of the address bus, the symbols with the maximum switching frequency are received, and at the second and subsequent bits, the switching frequency is twice as rare as the previous bit. Consequently, in the first cycle of operation, under the most severe conditions, the first bit of the address bus is checked. The considered codes coincide with the ordered address codes formed in the pulse counter of the known device, then an additional test program of address sampling is formed in accordance with the purpose of the invention. With the end of enumeration of all states of the counter 2 pulses (the end of the first control cycle), the output of the decoder 3 generates a signal of the end of the cycle, which passes through the driver of 4 pulses and resets the counter of 2 pulses, the generator 5 clocks, register 10 numbers, as well as through the driver 6 The pulses will switch to the next state the block 7 of the initial code setting (i.e. in the shift register 28 the information will shift to the right by one bit). At the same time, at outputs 17 of block 7, the initial code will be set to 20 ... 17 16 ... 4321 O ... O O ... 0010, which is the first informational check and address stimulus sent to the block under test with numeric outputs 20 and address outputs 23 devices. With anapogy with the first cycle of operation, the block 8 of adders, when interacting with the switch, the 9th number and the register of the 10th number, will form a sequence of codes, which will look like the tact number 20 ... 17 16 ... 4321 addresses. 1 0 ... O 0 ... 0010 2 0 ... O 0 ... 010C 4 0 ... O 0 ... 0110 6 p., O 0., 1000 8 0 ... o 0 ... 1010 10 N-1 0 ... 1 1 .., 1110 N-2 From this test sequence it can be seen that a constant zero potential arrives for the first bit of the address busses, for the second bit a sequence of codes arrives at the maximum the switching frequency, to the third and subsequent bits, the switching signals are twice as rare as the previous discharge, i.e. in the second control cycle, there was a shift of the entire code combination by one bit in the direction of the higher bits. Similarly, in the third cycle of monitoring, the initial information will be shifted in block 7 of the initial code setting. This will cause a corresponding shift of the entire code combination by one bit. Consequently, in the third cycle the code sequence with the maximum switching frequency will be supplied to the third bit of the address bus, and for each subsequent bit the switching signals will be received less than twice previous. Thus, in each new monitoring cycle, the signals with the maximum switching frequency in the next address bit will be shifted. Through K control cycles, the signals with the maximum switching frequency (where K is the block size of the 7 initial code) will arrive again for the first digit of the address. . In the prototype K 20. Thus, unlike the known device, for twenty complete control cycles, each address bit will be checked for the maximum frequency of input signal change, which will reliably give an opinion on the correspondence of the dynamic parameters to the technical characteristics of radio electronic tew. In addition to the main task of the Formation of an additional program I PMPGZHI. H. Ireso, the introduction of the switch 14 of the address of the PoBilo address and the process of fixing the outputs of the counter 7. pulses in the 1 or ft position in the diagnostics of malfunctions, when the addresses in the checked block are selected in order Actually, in the 5th case it is often necessary to set one or another digit of the counter to position 1 or O, but all other bits of the counter 2 pulses must operate in the counting mode. In order to form the ordered address codes, it is necessary to turn off the switch 36 in the address switch 14. In this case, the passage of signals from the output 21 of the counter 2 pulses to the address outputs 23 of the device is permitted. If the operator, the diagnostics wire detected in the malfunction being checked, sets any toggle switch in address setting block 1 to position 1 or O, then output 23 of the corresponding bit of switch 14 addresses will also have potential 1 or O. I Consider this more on the example of the first digit. If the first tumbler in block 1, the address setting is set to O, then the installation S-input of the counter 2 pulses will be connected via a toggle switch to the logical bus O, which will cause the installation of 1 pulse 2 of the counter 2 pulses, this will ensure that the counting pulse passes through transfer chains in the next bits. Consequently, all other high-order bits (in our case 2 ... 16) will work in the counting mode. From the corresponding first 22 outputs of the address setting block 1, the zero potential will go to the second input of the first element of the group of elements AND-NOT 34 in the address switch 14. As a result, at the output of this element, the NAND will be 1, at both inputs of the first element of the NAND, a group of elements of NAND 35 will have unit potentials, and at the output - O If the same (first) toggle switch is set in block 1, the address is set to 1 at the output 2 of the counter 2 pulses, as in the case of installation in O, will be., But with the corresponding output 22 peshesh. And .h ;. n difference ot ustatyukpkp and (1,, -i / urNIChGG, Sl (, (- 1нн.1. 1,

dah of the first element of the NAND group of elements of the NAND 34 will be unit potentials, and the output will be zero. In this case, the output of the first 23 bits will be 1, and the other bits will switch according to the switch bits of the counter 2 pulses.

Thus, the entered address switch 14 performs two functions — the main one — to provide an additional address sampling program and an auxiliary — to lock the bits of the address outputs in the O or 1 position when troubleshooting the tested block.

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Claims (1)

DEVICE FOR TESTING TESTS by ed. St. No. 1038926, characterized in that, in order to increase the reliability of control and expand the scope of the device, a mode switch and an address switch containing groups of second, third and fourth AND-NOT elements, an element NOT connected to the first inputs of the second elements are introduced into it AND NOT, but with an output - to the first inputs of the third AND-NOT elements connected by second inputs with the corresponding second outputs of the address setting unit, by third inputs - with the corresponding bit outputs of the pulse counter, and outputs - from the first and vho-. Dams of the fourth AND-NOT elements connected by the second inputs to the outputs of the second AND-NOT elements connected by the second inputs with the corresponding outputs of the number register, and the first inputs through the sharp switch with the logical buses 0 and § Logical 1, and the outputs of the fourth elements AND are NOT address outputs of the device. SU „1141379