SU1424020A1 - Test generator - Google Patents

Abstract

The invention can be used in the equipment for monitoring and diagnosing microprocessor programs; Controllers and microcomputers for generating pseudo-random sequences of test actions with specified properties. The purpose of the invention is to increase speed. The test actions generator contains shaper 1 pseudo-random numbers, memory block 2, switch 3, element 4, counter 5, trigger 6, and resistor 7. When. generation; the test provides for enumeration of all combinations of sequentially given commands of the microcomputer being tested from a certain number of allowed commands. Enumerating all combinations creates the conditions for detecting pseudo-unstable faults. 1 il. with (L

Description

//,,

ten

15

20

25

The invention relates to automation II computing technology and can be used to control microcomputers.

The purpose of the invention is to increase speed.

Pa drawing shows a block diagram of the generator.

The generator contains shaper 1 pseudo-random numbers, memory block 2, switch 3, element 4, counter C, trigger 6, resistor 7, memory block outputs 8, pseudo-random number generator outputs 9, generator start input 10, generator synchronization input 11 , the input 12 of the switch synchronization, the outputs 13 of the test generator set floor, the input 14 of the generator reset, the output 15 of the sign of the end of the generator test.

Shaper 1 is a linear feedback shift register and is implemented on standard logic elements.

Switch 3 contains a group of repeaters with three states, the outputs of which are 11) and are a group of information inputs connected to input 8 and a group of outputs connected via outputs 13 to a group of information outputs, and the control inputs of the group of repeaters are connected to input 12 switches 3.

The memory unit 2 can be executed in the form of a permanent or semi-permanent memory, where command codes of the installation sequence are distributed to the cells with addresses determined by the states of the shaper 1 pseudo-random numbers in the first N steps of its operation. The remaining cells of block 2 are filled with codes of microcomputer commands (where N is the number of installations of the computer being tested).

The generator works as follows.

Shaper 1 and counter 5 are reset by resetting their inputs with a general reset from device 14. The signal at this input can be formed automatically after the power is turned on or, for example, appears as a result of pressing the corresponding button on the control panel. Zero signal from the output of the counter 30 loan

35

40

45

50

0

five

0

five

-

0

five

0

five

0

When 5 arrives at the setup input into the On flip-flop 6 and sets it to the zero state, as a result of which the signal, at terminal 15, the device takes a zero value.

When a signal arrives, the sampling cycle of the command at input 11 of the device opens element 4, the synchronization signal comes from the synchronization input 10 of the device to the synchronization input of the shaper 1 pseudo-random numbers and counter 5, translating them to the following states, and the address code of the first command comes from the shaper 1 outputs pseudorandom numbers on the corresponding inputs of the group of address inputs of memory block 2. At the same time, the signal. The sampling cycle of the command enters the input of the chip's selection of the memory block 2 and the control input 12 of the switch 3, translating the repeater of this switch into a high-impedance state. The first command comes from the output of block 2 memory and through the circuit input 8 - outputs 13 to the outputs of the generator. After the signal is removed, the cycle of selecting the command And 4 is closed, prohibiting the cooling of the clock signal to the clock inputs of the pseudo-random number 1 generator and the counter 5, the output groups of the memory block 2 are set to a high-impedance state, the group of repeaters of the co-switch 3 is opened and the information from the output of the coder 1 Pseudo-random numbers arrive at the outputs of the device.

Thus, at the moment of setting a single signal value, the command sampling cycle changes the state of the t-pseudo-random number generator and counter 5 by one step and information on the outputs 8.13 comes over the buses from block 2, and when the shaper 1 state of the pseudo-random number is set the numbers and the counter 5 do not change, the information on the outputs comes from the second group of outputs of the bits of the pseudo-random number generator, which can be interpreted respectively as the first, second and subsequent words of the command into the diagnostic microcomputer.

After 2 steps of counter 5, the signal from the k-ro discharge of the counter enters the synchronous input of trigger 6 and translates it into a single state, which indicates the end of the installation sequence; (- commands and commands - control. 1H microcomputer.

The discharge counter 5 determines the length of the test action sequence, at the time of its overflow, the null signal from the reverse transfer output arrives at the installation input at the O flip-flop 6 and sets it to the zero state, as a result the signal at the device output 15 takes a zero value, which indicates the end of the sequence of test actions.

The efficiency of using the test actions generator to control the microcomputer is determined not only by providing a complete brute force command, but also by the ability to generate a sequence of test exposures containing all possible combinations of r (r - natural number) of n commands, as well as combinations of each of the n commands with all data sets, which provides control of the mutual influence of the circuits of microprocessor large integrated circuits and microcomputer elements.

For example, to ensure pairwise combination of all commands, the organization of the first and second groups of outputs of the pseudo-random number generator is performed by connecting the output lines of bits. Since the shaper of random numbers has 2–1 states, where k is the number of bits of the shaper, i.e. at its outputs all code words are formed, with the exception of zero (0000 is the forbidden state), then each state of the second group of outputs of bits (L, A) will be combined with all the states of the first group of outputs of bits (L, Aj ). Thus, this command address AjAj code will be encountered with a full set of | | 1x data. At the next step of shifting information in the pseudo-random number generator, the state will be interpreted as the address of the next command and, therefore, with a full cycle of operation of the pseudo-random number generator, it will ensure corresponding pairwise search of all commands. To provide brute force of 3.4 n. teams need to organize the first and second group of exit

shaper pseudo-random numbers by connecting, respectively, the outputs of each 3.4, etc. bits of the pseudorandom number generator. The use of the invention allows the formation of sequences of pseudo-random test effects for microprocessor-based programmable controllers and microcomputers. The repetition rate of commands in the output sequence of the test effects of an arrangement can be set by storing each command into several cells in block 2 of the instruction memory in accordance with a predetermined probability of repetition.

20

Claims (1)

Invention Formula A test generator containing a shaper of pseudo-random numbers, a memory block and a counter, the generator clock synchronization is connected to the first input of the I element, the generator reset input is connected to the reset inputs of the pseudo-random number generator and the counter, TL and h y and fi c in order to increase speed, the generator contains an element H, and a switch, and the synchronization input of the generator is connected to the memory synchronization, the output of which is connected to the first information input of the switch, the output of which is output A generator set, the output of the end of test sign is connected to the trigger output, the reset input of which is connected to the counter loan output, the k-th bit output of the counter, where k, N is the length of the installation sequence, taking into account the specific type of test set object, connected to the CJ trigger synchronization input, the information input of which is connected to the generator single potential bus, the counting input of the counter is connected to the output of the element And with the synchronous input of the pseudo-random number generator, the first and second groups of outputs of which are respectively connected with the address group of inputs of the memory block and the second group information inputs of the fottapom, and the second input of the element I is connected to the start input of the generator.