SU1136169A1 - Device for testing check of digital units - Google Patents

Abstract

A DEVICE FOR TEST CONTROL OF DIGITAL BLOCKS, containing a memory block, the first group of information outputs of which is connected to the first group of information inputs of the test register through a block of elements, the second group of information inputs of which is connected to the second group of information outputs of the memory block, where n is the number of outputs of the monitored block), the elements of AND, characterized in that, in order to improve speed, it contains a group n of switches of features, a group of n formers units a signal, a group of n zero signal conditioners, a prohibition element, each bi-directional output of the monitored unit connected to the outputs of the corresponding single and zero signal generator groups and the first input of the corresponding group comparison circuit, the second input of which is connected to the first output of the corresponding feature switch the parameters of the control signals of each of which are connected to the group of outputs of the register of tests, the clock inputs n of the switches of the attributes of the coi group ineny clock input of the first device, the first and second outputs of each switch group are connected signs Q inputs of the respective formers unit group and zero signals, outputs the comparison circuits are connected to sootg group; The corresponding inputs of the first element AND, the output of which is connected to the first input of the prohibition element, the second input and output of which are connected respectively to the first output of the second group of information outputs of the memory block and the first input of the second element AND, the second input of which is the second clock input of the device, and the output is connected to the blocking input O9 O) the house of the block of elements I. O) from

Description

The invention relates to computing and can be used in the equipment for controlling digital blocks of quasi-electronic PBXs under mass production conditions with a large range of digital blocks. A device for controlling logic circuits is known, comprising an input unit, a task register, digital-analog and analog-digital converter units, a comparison unit, a control unit, a display unit, a unit of standards, a mask register and switch 1.

The disadvantage of the device is insufficient performance.

The closest to the proposed technical entity is a multi-channel test control device for digital computer nodes containing an input unit, a memory unit whose address outputs are connected to the test register through the address transmission unit, a display unit, a clock generator, one output connected via an AND element with the input of the address counter, and the other output with the reception-transmission unit and through the second element I with the gate input of the address transmission unit, the output of the address counter is connected to the address inputs of the memory block and 2.

A disadvantage of the known device is the presence of switching fields that are not controlled by the storage device, which creates difficulties in reprogramming and reduces speed.

The purpose of the invention. - increase the speed of the device.

The goal is achieved in that a device containing a memory block, the first group of information outputs of which is connected to the first group of information inputs of the test register through the block of elements, the second group of information inputs of which is connected to the second group of information outputs of the memory block, group n of circuits comparisons (where n is the number of outputs of the monitored block), elements I, a group n of switches of attributes, a group of n formers of a single signal, a group of n formers of a zero signal, an element the prohibition, each bidirectional output of the monitored unit is connected to the outputs of the corresponding generator of the single and zero signals of the group and the first input of the corresponding comparison circuit of the group, the second input of which is connected to the first output of the corresponding switch of the group signs, four inputs of control signal parameters of each of which are connected to the group of outputs the test register, the clock inputs n of the switches of the signs of the group are connected to the first clock input of the device, the first

and the second outputs of each switch of the group signs are connected to the inputs of the corresponding shaper units of the single and zero group signals, the outputs of the group comparison circuits are connected to the corresponding inputs of the first element AND whose output is connected to the first input of the prohibition element, the second input and output of which are connected respectively to the first output of the second groups of information outputs of the memory block and the first input of the second element I, the second input of which is the second clock input of the device, and the output is connected to the block yuschim input block elements I.

FIG. 1 shows a block diagram of a multichannel test control device of digital units CE ATS; in fig. 2 - time diagram of the device; in fig. 3 is a block diagram of the control algorithm.

The device contains a monitored block 1, an input block 2, a memory block 3, an address counter 4, a test register 5, an AND block 6, a group n of comparison circuits 7, a reception-reception block 8, a first And 9 element, a prohibition element 10, a second the element And And, the generator 12 clock pulses, the element And 13, a group of switches 14 signs, a group of drivers 15 single signal, a group of drivers 16 zero signal and block 17 of the display.

The device works as follows.

The test program of the monitored block 1 is entered from block 2 of input to block 3. The monitored block 1 is connected and after the Start command formed in block 2 of the input, the counter 4 of the address, prohibition element 10 and test register 5 are reset. Counter 4 of the address controls the operation of block 3, which outputs the contact address code of the tested block to block 6 of the AND elements and the test code, which are written into the test register register 5. The test code determines the type of measurement and input action, sets the operation mode of this contact of the monitored unit 1. After the initial setup of the register of 5 tests, the initial state code is written in the register cells. All drivers 15 and 16 are closed and have a high impedance condition.

The check of blocks is made according to the control program stored in block 3 and representing the following sequence of words containing the command code and contact number.

Part 1 is a setup program for test-unit modes. In the register register 5 tests, respectively, the input command code is supplied from block 3 to the inputs of the test block. This opens the formers 15

or 16, providing the true potentials of the logical "1 or logical" O at the input contacts of the monitored block, and the input of the comparison circuit 7 from the switch 14 receives the indication of control of a given level. Item 10 prohibition is disabled. Control command codes are written to the test register register cells 5 corresponding to the outputs of the monitored block I, while the output drivers 15 and 16 remain in the closed state. The inputs of the comparison circuits 7 receive the sign of the control of the logical state of the switch 14. On the falling edge of the exit sign coming from the first output of block 3, in the element. 10 prohibition, a trigger is triggered, permitting the prohibition element to operate in the presence of a unit potential at the first output of block 3.

The following is the control program - part 2 of the program. At the same time, at the output of block 3, in cycle 1g, a word from the next cell of block 3 appears, containing information on the state change on one of the inputs of the tested block. The unit level from the first output of block 3 permits the operation of the prohibition element and the record of the change in the contents of the register cell. 5 tests, i.e. acting on the input of the monitored block, will arrive at the leading edge of the following pulse in tj cycle through element 11 and block 6 of elements AND, if on all contacts of the tested block the logic levels correspond to those recorded in the cell of the register 5 tests. (Otherwise, a zero potential appears at the output of the inhibit element, which prohibits the passage of t2 to write information to the register of 5 tests and And 13 to advance the counter of 4 addresses). Then, in the register cells of the 5 tests / matches, corresponding to the outputs of the monitored unit, information about the changes in the output signals is entered.

Information on the test progress is displayed on the display unit: check point in the event of a fault, contact numbers where the measured signals do not correspond to the program.

0 The proposed control process control system increases the speed of the device, eliminates manual switching during the control, and during changeover increases the control reliability, because

5 input effects and output signals are monitored on all channels simultaneously.

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Claims (1)

DEVICE FOR TEST MONITORING OF DIGITAL BLOCKS, containing a memory block, the first group of information outputs of which through the block of elements And is connected to the first group of information inputs of the test register, the second group of information inputs of which is connected to the second group of information outputs of the memory block, group η comparison circuits (where η - the number of conclusions of the controlled unit), AND elements, characterized in that, in order to improve performance, it contains a group η of feature switches, a group of η unit formers a signal, a group η of zero-signal conditioners, an inhibit element, each bi-directional output of the monitored unit being connected to the outputs of the corresponding single and zero signal former of the group and the first input of the corresponding group comparison circuit, the second input of which is connected to the first output of the corresponding group attribute switch, four parameter inputs control signals of each of which are connected to the group of outputs of the test register, the clock inputs η of the switches of the characteristics of the group are connected to by the device’s clock input, the first and second outputs of each group attribute switch are connected by q inputs of the corresponding unit and zero group signal drivers, the outputs of the group comparison circuits are connected to the corresponding inputs of the first AND element, the output of which is connected to the first input of the inhibit element, the second input and output of which connected respectively to the first output of the second group of information outputs of the memory unit and the first input of the second element And, the second input of which is the second clock input trinity, and the output is connected to the blocking input of the block of elements I.