RU1793458C - Device for displaying information on gas-discharge indication ac board - Google Patents

Abstract

Usage: in computer technology. Summary of the invention: the device comprises: a gas-discharge indicator panel 9, counters 2, 13 and 18, an oscillator 3, a clock pulse generator 4, a random access memory block 15, read-only memory blocks 16 and 21, keys of the first group 8, keys of the second group 7, shift registers 5 and 6. Elements NOT 19, multiplexers 11, 14 and 22, write-read control unit 12, element 23, line formation control unit 17.4-12-17-18-21-21-20-20-8 -9.4- 23-17-2-3-11-15-22-5-6-7-9, 12-13-16-14-15, 10-11, 10-21.2 ill.

Description

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The invention relates to automation and computer technology and is intended for use in information display devices built on gas discharge panels of alternating current.

A device for controlling a gas discharge indicator panel comprising a pulse generator, an OR-NOT element, a horizontal pulse counter, a vertical pulse counter, a first memory unit, a second memory unit, a character generator, an exclusive OR element, a trigger, a forming unit write / erase pulses,

The disadvantage of this device is the presence of a second memory block and exclusive OR elements that perform a comparison function. Since in the second memory block it is necessary to store information about the state of each element of the gas discharge panel recorded in the previous recording cycle, and compare it with the current information, which leads to an increase in the processing time of the information and a decrease in speed.

A device for displaying information on a gas discharge display panel and a device for outputting information comprising common features of a read-only memory unit, a switch, a shift register, a matrix indicator, a clock, a fragment number counter, and a scan unit are also known.

The disadvantage of these devices is their low speed, because for image playback, it is necessary to record information on the state of the entire panel in the memory unit and repeatedly access the same memory cells to display fragments of the image of familiarity columns when reading information to obtain information character string. These devices, in combination with a high-speed channel for transmitting information of the Manchester-P type, are not advisable to use because of the need to receive one information word from the communication line per exchange period, which also leads to a loss of speed.

A device for outputting information is known, comprising a control unit and generating information, an address decoder, a data register, a buffer register of an indication mode, a register of an indication mode, an increment counter in X and Y, two NAND elements, two NOT elements, a data transfer trigger , account trigger, three keys, column, row counter, increment trigger, register of the first and second coordinates,

NAND, t.fOK simple symbol raster memory, complex symbol memory block, multiplexer, EXCLUSIVE OR, shift register whose advantage is the increase in the speed of information output to the panel screen, achieved by parallel measurement of the X and Y coordinates determining the place of the occupied elementary point on the GUI panel.

However, its drawback is the need to simultaneously change the two coordinates X and Y at once, repeatedly scan the character image that is stored in the memory unit and add up the increment at the X coordinate on the increment counters, which together limits the performance of the display device.

The closest technical solution for the number of signs and technical. essence of the device is a device for displaying information on the gas discharge indicator panel of the GUI, which is taken as a prototype, containing a clock pulse generator, counters: familiarity, image fragments, line addresses, two multiplexers, character generator, random access memory, the first constant block memory, first shift register, keys of the first group, keys of the second group, indicator panel, decoder, selector, the advantage of which is the increased reliability of the device by introducing a memory unit The information register and familiarity counter that define the selected familiar-. hundred on the GUI panel. However, its disadvantage is insufficient performance due to the need to repeatedly access the addresses of the panel lines in the current line.

An object of the invention is to increase speed.

This goal is achieved by the fact that in the device for displaying information on a gas-discharge display panel of an alternating current containing a clock, three counters, two multiplexers, a character generator, random access memory, the first read-only memory, the first shift register, the outputs which are connected to the corresponding control inputs of the keys of the first group, the outputs of which are connected to the horizontal buses of the gas discharge indicator panel, the vertical buses of which are connected to the outputs of the keys For any group whose control inputs are connected to the outputs of the decoder, the output of the RAM block is connected to

information input of the first multiplexer, the first address input of the character generator is connected to the output of the first counter, and the output is connected to the first information input of the second multiplexer, the gate inputs of the keys of the first and second groups are the gate inputs of the device, the selector, the information input of which is the information input of the device.

In addition, a second read-only memory unit, a second shift register, a write-read control unit, a third multiplexer, an AND element, a line forming control unit, NOT elements, the outputs of which are connected to the information inputs of the decoder, and the inputs are connected to the address inputs of the second permanent unit are introduced memory and with the outputs of the second counter, the information inputs of which are connected to the outputs of the second block of read-only memory, the installation input is connected to the first output of the selector and the control input of the second block of the remaining memory, the clock input of the second counter is connected to the first output of the line forming control unit, the first clock input of which is connected to the third output of the clock generator, and the second output is connected to the clock inputs of the first and third counters, the second address input of the character generator is connected to the information input selector, the second output of which is the Ready device, and the third output of the selector is connected to the control input of the second multiplexer, the second information input of which connected to the bus with zero potential, and the output is connected to the information input of the operational memory block, the control input of which is connected to the first output of the block, write-read control, the first and second clock inputs of which are connected respectively to the first and second outputs of the clock , the control input of which is the first control input of the device, the first output of the clock generator is connected to the first input of the element And, the output of which is connected to the second clock input of the unit the formation of the line, and the second input of the AND element is connected to the control inputs of the first memory block and the third multiplexer, the first control input of the line formation control unit, and the second output of the write-read control unit, the third output of which is connected to the clock inputs

the first and second shift registers, and the fourth output is connected to the installation input of the third counter, the outputs of which are connected to the information inputs 5 of the first read-only memory block and the write-read control unit and the first information input of the third multiplexer, the second information input of which is connected to the output of the first

0 of the read-only memory block, and the output is connected to the address input of the random access memory block, the fifth output of the read-write control unit is connected to the second control input of the control unit

5 by forming a line, the third control input of which is the second control input of the device, the third and fourth outputs of the line forming control unit are connected, respectively, with the control and address inputs of the first multiplexer, the first and second outputs of which are connected to the information inputs of the first and the second shift registers connected to the corresponding control inputs of the keys of the first group,

In FIG. 1 is a structural diagram of an apparatus for displaying information on an AC discharge panel;

0 in FIG. 2 - time diagrams of the operation of the device.

The device for displaying information includes (see FIG. 1) a first counter 2, a character generator 3, a clock pulse generator 4, a first shift register 5, a second shift register b, a block of a first group of high voltage switches 7, a block of a second group of high voltage switches 8, a panel 9, a selector 10, a second multiplexer 11, a read-write control unit 12, a third counter 13, a third multiplexer 14, a random access memory block 15, a first read-only memory block 16, a line forming control unit 17, a second counter 18,

5 elements NOT 19, decoder 20, second read-only memory block 21, first multiplexer 22, element 23, outputs of the first counter 2 are bitwise connected to the first address inputs of character generators 3,

0 the second address inputs of the character generators are connected to the information inputs of the device .. The control input of the clock pulse generator 4 is connected to the first control input of the device, the clock input of the first shift register is supplied with the clock input 5, and the outputs are connected to the first control inputs of the first key block of the first group 7, write clock pulses are applied to the clock input of the second shift register 6, and the outputs are connected to the second control inputs of the keys of the first group 7, the first gate input of the keys first of group 7, gate XI is applied, and the fourth gate input, gate X2, from the gate input of the device, the outputs are connected to the first inputs of the gas discharge panel 9, gate YI is fed to the first gate input of the keys of the second group 8, and gate Y2 is the second gate , from the gating input of the device, the outputs are connected to the second inputs of the gas discharge panel 9, the information inputs of the selector 10 are bitwise connected to the information inputs of the device, the second output is connected to the output of the device Ready, the first information inputs are second the second multiplexer 11 is bitwise connected to the outputs of the signs of the generator 3, the signal Zero is applied to the second information inputs, the control input is connected to the third output of the selector 10, the information inputs of the RAM unit 15 are bitwise connected to the outputs of the second multiplexer 11, the address inputs are the bottom is connected to the outputs of the third multiplexer 14, the outputs of the first block of read-only memory 16 are bitwise connected to the second information inputs of the third multiplexer 14, the first information inputs of the third multiplex Ora 14 are bitwise connected to the information inputs of the first read-only memory block 16, to the outputs of the third counter 13 and to the information inputs of the write-read control unit 12, the second clock input of the write-read control unit 12 is connected to the second output of the pulse generator 4 , the first output of the pulse generator 4 is connected to the first clock input of the write-read control unit 12. The first output of the write-read control unit 12 is connected to the control input of the RAM block 15, the second output is connected not with the control input of the third multiplexer 14, with the control input of the first block of read-only memory 16, the outputs of the decoder 20 are bitwise connected to the third information inputs of the block of keys of the second group 8, d the outputs of the second block of read-only memory 21 connected to the information inputs of the second counter 18, the outputs of the second counter 18 are connected to the inputs of the elements HE 19 and to the address inputs of the second block of read-only memory 21, the control input of the second block of read-only memory 21 is connected to the first output of the selector 10 and with tanovo input of the second counter 18, output

element And 23 is connected to the second clock input of the formation control block. Lines 17, the third and fourth outputs of the block

formation control. Lines 17 are connected respectively to the control and address inputs of the first multiplexer 22, the information inputs of the first multiplexer 22 are bitwise connected to the outputs of the RAM unit 15, the clock input of the second counter 18 is connected to the first output of the formation control unit of line 17, the second control the input input of the control unit for forming the line 17 is connected to the fifth output of the write-read control unit 12, the second output of the write-read control unit 12 is connected to the first control the input of the control unit forming the line 17, the first clock input of the control unit forming the line 17 is connected to the third output of the clock generator 4, the second output is connected to the clock input of the first counter 2 and to the clock input of the third counter 13, the first output is the output of the BEGINNING device to the third control input of the control unit forming the line 17 the signal is PROHIBITED from the second control input of the device, the first input of the element And 23 is connected to the first output of the pulse generator 4, w the second input is connected to the first control input of the control unit for forming the line 17, the installation input of the third counter 13 is connected to the fourth output of the write-read control unit 12, the third output of the write-read control unit 12 is the output and connected to the input of the TAP device, the first the output of the first multiplexer 22 is connected to the information input of the first shift register 5, the second output of the first multiplexer 22 is connected to the information input of the second shift register 6, the information input of the soybean decoder 20 Inonii yield NOT element 19 is a line address information code.

The device operates as follows.

We will consider the operation of the device in three stages.

First step. Setting the initial state of the circuit when applying the supply voltage. The second is the receipt of the symbol code at the information input of the device, information is recorded in the RAM block, and the third is that after the information line is filled, the write-read control unit is automatically

issues a command to read information and display it on the panel.

When power is applied, the circuit is restored to the initial state at the outputs of the first counter 2, which unfolds the information received at the information input of the device in ten image lines, sets the zero address of the image fragment to the third counter 13, which forms the memory cell number of the RAM block 15. in the information recording mode, the recording address is also set to zero, which, through the third multiplexer 14, is supplied to the RAM block 15, which serves for temporary storage of the received and information information input apparatus and its generating line in the image.

The write-read control unit 12 generates control signals in accordance with the number of pulses received at the information input from the output of the third counter 13, putting it into recording mode, prohibiting the passage of the TI ZAP signal from the third output, and turning off the circuits associated with reading information and highlighting it to the panel, which includes the first read-only memory block 16, the line forming control unit 17, the second counter 18, elements NOT 19, the decoder 20,. the second read-only memory block 21, the first multiplexer 22, and waits for the first symbol code to arrive at the information input of the device.

Second phase. Upon receipt of information at the input of the device, an eight-bit data word appears - the code of the incoming character and, simultaneously from the first output of the selector 10, a high potential received at the control input 4, forming three sequences of pulses shifted one relative to the other by a clock cycle (Fig. 2) , assembled on a generator and controlled shift register. The symbol code is fed to the second address inputs of the character generator 3, which is a ROM and contains a set of characters that are displayed on the GUI panel, to the first address inputs of which the zero address of the image fragment is supplied, to the information inputs of the decoder 10, which compares the input information with permanently flashed and determines the presence of service characters line ending, line feed, editing previously recorded. With the arrival of the first pulse of the sequence (Fig. 2, b) to the control input of the RAM block 15, the data of the zero fragment of the image is recorded at the zero address. The first pulse of the sequence (Fig. 2. c) is supplied to the first clock input of the third counter 13 at the second output of which the first recording address is set. This address through the first information input of the third multiplexer 14 is fed to the address inputs of the random access memory unit 15. The same pulse with

The output of the character generator 3 reads the data of the first image fragment, which through the first information inputs of the second multiplexer 11 are fed to the information inputs of the operational

5 of memory 15, waiting for the recording permission signal to arrive at the control input. With the arrival of the second pulse of the sequence (Fig. 2b), data is recorded, thereby fragmenting the image to the corresponding addresses of the main memory block 15.

With the arrival of the last character of the line, that is, with the arrival of the 420th pulse of the sequence (Fig. 2, c), the write-read control unit 12 generates a low potential at the fifth output, received at the second control input of the unit - equalization by the formation of line 17, which determines the filling of the elementary

0 lines, for each forty-two filled characters, the low potential from output 2 prohibits the passage of pulse sequences (Fig. 2 b, c), respectively, and resets the control input to

5 first information inputs of the first block of read-only memory 16, which serves to form according to a certain law

 read addresses starting with senior

addresses minus ten in increments of ten

0 addresses, to the least significant bit - forty-two

times and repeat it ten times in mode

 outputting the generated information from the RAM unit 15 to the GUI, setting the read address to zero. So

5, the recording step is completed and the information recording / reading control unit automatically switches to the information reading mode and displays it on the panel.

0 The third stage. The presence of high potential from the second output of the control unit by recording by reading 12 at the control input of the first block of read-only memory 16 allows the address to be sampled

5 fragments of images, and the presence of the same potential at the control input of the third multiplexer 14 provides the transfer of this address to the address inputs of the RAM unit 15, to the control input of which there is a high potential from the first output of the write-read control unit 12. High potential at the control input of the RAM block 15 permits reading the data recorded at this address of the image fragment, which are fed to the information inputs of the block of the first multiplexer 22, significant for decomposing information into even and odd for three clock cycles and outputting it to the first and second shift registers 5, 6, assembled on sixteen eight-bit circuits 134IR8, connected in series to increase the bits to 128 and the first TI records received on the inputs of the shift registers 5, and b are written to these registers, and so on, the reading takes place before these registers are filled. At the same time, the pulse sequence (Fig. 2, a) is applied to the second clock input of the control unit by forming line 17, filling in the line by filling in every forty-two familiarities, that is, when forty-two pulses pass through. The first output is a negative polarity pulse, which is fed to the clock input of the second counter block 18, which generates a nine-bit information line code , which is inverted by the elements NOT 19. From the outputs of the first and second shift registers 5, 6, the information goes to the control inputs of the key block of the first group 7, assembled on 33 microcircuits 1109KN5B, which are a four-bit high-voltage a clear, three-level switch with an decoder at the input, to the gate inputs of which control signals of strobes X 1, X2 from the device are supplied.

From the output of the key block of the first group 7, the information goes to the main and auxiliary horizontal elements of the IGPV panel. 2.56 / 256 9. The nine-bit (low-order bit is straight and inverse) information line code is fed to the information inputs of the decoder 20, assembled in a two-stage scheme. The first stage is a decoder, assembled on eight chips 133ID31, to the inputs of which the remaining four bits of the line code are received. From the outputs of the code line decoder 20 we get 128 pulses corresponding to the number of the main vertical elements of panel 9, received at the control inputs of the second group 8, executed on 33 1109KN5B microcircuits, to the gate inputs of which control gates VI, V2 are fed. G output block high-voltage switches 8 excitation signals are fed to the vertical main and auxiliary electrodes of the IGPV panel 256/256 9, Thus

Thus, on the horizontal electrodes of the IGPV 256/256 9 panel there is information from the first (next) fragments of the image of the line, and when the excitation signal arrives at the vertical electrodes of the panel 9, these fragments are displayed. A complete display of the information line is carried out upon receipt of the second clock input 17 the formation of the line 420 pulses of the sequence5 (Fig. 2, a), upon receipt of the write-read control unit 12 from the output of the third counter 13 of the 421st pulse, this corresponds to that the circuit automatically returns to mode

0 records and awaits the arrival of the following information to the information input of devices. The work of highlighting the following information line is similar to that described above:

5 If there is one of the line control codes at its third output at the information inputs of the selector 10. there is a low potential, which is fed to the control input of the data multiplexer 11, the latter is transferred to the data transmission mode from the second information inputs, to which the low potential is constantly applied and fed to the information inputs of the operational unit

5 memories 15.

Further filling in the information line is carried out in the same way as when obtaining the character code, similar to that described above. Changing a previously recorded line of information (editing) is carried out with the arrival of the corresponding code, which sets the first potential low potential, which is fed to the control input of the second

5 of read-only memory 21, which pre-writes the offset code to the second counter 18, from the outputs. the last is removed the information line code received at the address inputs

0 of the second block of read-only memory 21, from its output a new code is fed to the input of the second counter 18, the internal counters are pre-set and a new information line code is generated.

5 The subsequent change of the information line code is carried out upon receipt of a pulse at the clock input of the second counter 18c of the first output of the line forming control unit 17. Further work on outputting information to

the panel is repeated according to the algorithm described above.

The additional introduction of distinguishing features into the prototype made it possible to significantly increase the output speed; the distinguishing features allow recording the entire information line of characters in the internal memory and preparing it for indication. In the considered prototype, reading the received information. The device for displaying information on a gas-discharge display panel of an alternating current containing a clock, three counters, two multiplexers, a character generator, random access memory, the first read-only memory unit, the first shift register, outputs which are connected to the corresponding control inputs of the keys of the first group, the outputs of which are connected to the horizontal buses of the gas discharge indicator panel, the vertical buses of which the second are connected to the outputs of the keys of the second group, the control inputs of which are connected to the outputs of the decoder, the output of the RAM block is connected to the information input of the first multiplexer, the first address input of the character generator is connected to the output of the first counter, and the output is connected to the first information input of the second multiplexer the key inputs of the first and second groups are the gate inputs of the device, a selector, the information input of which is the information input of the device, characterized in that, with To improve performance, a second read-only memory unit, a second shift register, a write-read control unit, a third multiplexer, an AND element, a line forming control unit, NOT elements, the outputs of which are connected to the information inputs of the decoder, and the outputs are connected to address the inputs of the second block of read-only memory and with the outputs of the second counter, the information inputs of which are connected to the outputs of the second block of read-only memory, the installation input is connected to the first output of the selector and control to the input of the second memory block, the clock input of the second estimator is connected to the first output of the line forming control unit, the first clock input of which is connected to the thirdformation, the input of the device from the memory blocks occurs symbolically, i.e., by filling in each familiarity about the string, which leads to the need for output

images of the string, resorting to multiple accesses to the same memory addresses where these characters are stored, repeated reading of characters from the internal memory increases the output time of the character string, which reduces the speed of such circuits.

him the output of the clock generator,

and the second output is connected to the clock inputs of the first and third counters, the second address input of the character generator is connected to the information input of the selector, the second output of which is the accuracy of the device, and the third output of the selector is connected to the control input of the second multiplexer, the second information input of which is connected to the bus zero potential, and the output is connected to the information input of the random access memory block, the control input of which is connected to the first output of the write-read control unit, the second and second clock inputs of which are connected, respectively, with the first and second outputs of the clock generator, the control input of which is the first control input of the device, the second output of the clock

connected to the first input of the And element, the output of which is connected to the second clock input of the line forming control unit, and the second input of And element is connected to the control inputs of the first read-only memory unit and the third multiplexer, the first control input of the line forming control unit and the second output read-write control unit, the third output of which

connected to the clock inputs of the first and second shift registers, and the fourth output is connected to the installation input of the third counter, the outputs of which are connected to the information inputs of the first

a read-only memory and a read-write control unit and a first information input of a third multiplexer, the second information input of which is connected to the output of the first

of the read-only memory unit, and the output is connected to the address input of the random access memory unit, the fifth output of the write-read control unit is connected to the second control input of the control unit

line forming, the third control of the first multiplexer, the first and second

whose input is the second control outputs of which are connected to the information input of the device, the third ion inputs, respectively, of the first and

the fourth outputs of the control unit fore-second shift registers, the outputs of which

By string expansion, they are connected appropriately-connected to the corresponding control of the juvenile with the control and address input inputs of the keys of the first group.

FIG. 2