SU1603365A1 - Data displaying device - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in information systems for outputting the displayed information from a computer to a gas discharge plasma panel. The purpose of the invention is to increase speed. The goal is achieved by introducing a shifter, cycle trigger, write and erase triggers on X and Y coordinates, two buffer registers, address register, and AND element, which splits the character into the minimum number of elements and reduces the number of calls from the computer. 2 Il.

Description

This invention relates to automation and computing and can be used in various systems to display the displayed information from a computer to matrix graphical indicators with internal memory.

The purpose of the invention is to increase the speed and simplify the interaction with the computer-based device to display information by splitting the characters into the minimum number of elements, ensuring the minimum display time of the element and minimizing the number of hits from the third-party computer.

In Fig. 1, the structural scheme of the proposed device is inserted; in FIG. 2, the timing diagrams of its work.

The device contains a gas discharge in, a dikatornu 10 panel (happ) 1 alternating current, keys of the first 2 and second 3 groups, blocks 4 and-5 of the registers, respectively, in the X and Y coordinates, first element 6, decoder 7 records (in registers) , synchronizer register 8, permanent memory unit 9 (ROM), pulse counter 10, recording mode trigger 11., erase mode trigger 12, clock impulse generator 3, mapping board 14 components, shifter 15, increment counters 16 coordinates, the second element. And 17, the counter 18 shifts, the trigger 19 cycle, the element OR-NOT 20, the decoder 21 controls, the trigger 22 records on the coordinate X, the trigger 23 records on the coordinate Y, the trigger 24 erase on the coordinate X, the trigger 25 erase on the coordinate Y, the third 26 and fourth 27 And elements, the first 28 and second 29 buffer registers, the Fifth 30 and sixth 31 And elements, ready trigger 32, address register 33, address selector 34, select trigger 36.

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device, the seventh element And 36, the key 37 (signal response device), the data input 38, the first and second grzgpu address addresses 39 and 40, input 41, the device address setting, the input address writing 42, the data recording input 43, output 44 device response.

The device for displaying information allows forming an image on the screen of the HIPP in the minimum number; 0 cycles of operation of the panel. This is achieved by dividing the characters into elements in such a way that each character element is formed at the intersection of the selected display electrodes X and Y, and more than one display electrode can be selected both in the X coordinate and in the coordinate Y. .

In the device for displaying information, the addressing system of the display electrodes is implemented, allowing 25 for two calls from the control computer to form an image of the X D format at an arbitrary location of the HIPP. For this, in the address area of external computers; The zones of the recording zone X, the recording zone Y, the erase zone X and the erase zone Y are assigned to each zone. Each display electrode has one address; in the recording and labor zones, the adjacent electrodes have corresponding addresses. The size of the recording and erasing zones is equal to the number of GIPP electrodes at the corresponding coordinates. With one reference from the control computer, D neighboring elec- trodes of the X or Y electrodes can be selected, the address portion of the reference from the computer determines the position of the image element in one of the coordinates on the HIPP screen with a single-electrode resolution, and required electrodes. This is achieved by introducing a shifter, which shifts the incoming data to its inputs by a number determined by the lower bits of the address part of the call from the control computer, and writes the shifted data to the neighboring registers of the X or Y registers, for which the coordinate increment counter is applied, the second element is AND, the counting of shifts. and the trigger cycle.

The device for displaying information operates as follows.

The initial state is the mode of maintaining the HIPP discharge, in which the keys of the first 2 and second 3 groups produce uninterrupted sequences of discharge support pulses arriving at the vertical and horizontal ELECTRODES of the panel. In the mode of maintaining the bit on the outputs of the flip-flops 11 and 12 of the write and erase modes, the levels are low, and the ROM 9 generates the bits maintain signals, the incoming data inputs of the register 8, which serves to eliminate the interference on the outputs of the ROM 9, when switching its address inputs, The shape of the signals at the outputs of the keys of the first and second groups is determined by the shape of the control signals and in the mode of maintaining the bit does not depend on the state of the inputs of these blocks of keys X and Y. The cycle of the display of the T 20 ISS indication board is divided into 32 clocks. The period of the clock frequency is 0,625 ISS. It is set by the clock pulse generator, and the five-bit synchronizer binary counter, through the first group of address inputs, alternately swaps ROM cells, which encode the X and Y key group control signals, write stubs, erase and end recording and erase modes. Yes, write and erase gates are output to the recording inputs of the write mode trigger and erase mode trigger, respectively. Since in the bit hold mode, the bottom of the data inputs of these triggers are set Kie levels. When the recording gates and erase gates arrive at the outputs of the triggers, the levels remain low, and the mode of maintaining the discharge continues. As soon as the data input of one of the recording and erase modes triggers is high, which can happen when either the trigger 22 and trigger 23 are installed, or the trigger 24 and trigger 25 are set, the corresponding trigger of the recording mode or erase is set when the gate arrives recording, the ROM is switched by the second or third address input to the generation of the write or erase signals. In the recording and erasing modes, recording and erasing signals are generated, and the shape of the signals at the outputs of the X and Y key groups depends on the data inputs. This provides

selective recording and erasing of image elements located at the intersection of the selected display electrodes. The display electrodes are selected at high levels at the data inputs of the key groups, except for the X keys in the recording mode, which necessitates the inversion of data at the outputs of the registers of the X group in the recording mode. At the end of the write cycle (erase) of the ROM, a strobe of the end of the write mode (erase) is generated, which clears the triggers 11 and 12 of the write mode (erase), blocks A and 5 of the registers X and Y, the triggers 22-25 of the record (erase) X and Y. After this, the display panel is ready to display the next element.

In the write and erase modes, the operation of the device for displaying information is subdivided into the process of accessing the device from the control computer with writing information to the buffer registers and to the process of reading information from the buffer registers with the control of the display panel. Figure 2 shows time diagrams of the device operation for displaying information: a - the state of the first 39 and second 40 address inputs of the device; b - state of data inputs 38 of the device; c - signal recording address of the device 42; g - data recording signal of 43 devices; d - 44 device response signal; e is the read enable signal from the first and second buffer registers at the output of the fifth element AND .30; W - signal at the output of trigger 19 of the cycle; .3 - signal at one of the outputs of the decoder 7 records in the registers; and - a signal to confirm the record in the group registers at the input of the first element AND 6j to - the signal at the output of the shift counter 18; l - data at the output of the shift- tel 15; m is the trigger state 22 of record X; n is the state of trigger 23 of record Y; o is the read blocking signal from the buffer registers at the output of the element OR NOT 20; p - strobe of the end of the record and erase modes at the fourth output of the synchronizer register 8..

Writing information from the control computer to the buffer registers is as follows.

The control computer sets the address on the address inputs of the device, then sets the low level

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at the input of the address recording signal, at which the trigger is set, the device selection, if the 15–11 address bits match the code set at the device address setting inputs, the younger part of the A10-AO address is written to the address register 33, the state is written No output element And 31 in the trigger 32 ready. If the buffer registers are full, set the output resolution at low levels, so the output of the sixth element is also low. The readiness trigger 32 is cleared and blocks the operation of the AND 36 element until a high level appears at the write resolution of the first and second buffer registers, in which case the readiness trigger is reset. After setting a low level at the input of the entry, the address of the computer device removes the address and sets

5 data at the information input of the device, after which it sets a low level at the input of the device data record. In case the readiness trigger is set, the output

The element n 36 appears high, which writes data to the first buffer register 28 and writes the address from register 33 adres to the second buffer register; at the output of the device’s response, a low level is established, according to which the computer sets a high level at the input of the device’s data recording, which in turn leads to a high level at the output of the device’s response and the end of the recording processes in the first and second buffer registers, The fact that the readout outputs of the buffer registers appear high levels signaling the availability of information at the data inputs. The control computer takes the front of the device response, removes data and sets a high level at the output of the device address record. At this time, one cycle of access from the control computer to the device for displaying information ends. The following computer references are similar to those described.

The process of reading information from the buffer registers begins if the output level of the I-30 is set to a high level, what happens

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in the presence of high levels at the outputs of the resolution of reading buffer registers and at the output of the element OR NOT 20, i.e. when the display board is in the hold mode. The front of the signal at the output of the AND 30 writes into the counter 16 increments of coordinates of the address bits A8-A4 and sets the trigger 19 of the cycle. At this time, data from the first buffer register is set at the data inputs of the shifter 15, A3-AQ bits are set at the address inputs, and a low level from the code of the shift counter 18 is set at the control input. Therefore, at the output of the shift block, the youngest part of the data shift is set. A high level from the cycle trigger output goes to the second input of the element And 17, the output of which is set to a high level, since the first input of the element And 17 also has a high level from the output of the element 6. The high level goes to the control input of the decoder 7 entries in the registers and on one of its steps a low level is set, which writes data into the selected register of registers of groups X or Y. After the recording is done, the output of the registers of the group HiliU is set to low. Ram, due to which the output of the AND element 6 is also set low, which leads to the establishment -on low level output of the counter 18. translations. The high level from the output of the shift counter switches the shift block to the higher part of the shift data at the output of the shift block and increases the state of the counter 16 of the increment of coordinates by one. At this time, the control input of the register decoder 7 is set to a low level, which leads to the installation of high levels on all outputs of the decoder, which leads to the installation of high levels at the output of the register entry register X or Y at the output of the And 6 element. Now, at both inputs of the And 17 element, the high levels are set and the formation of the second impulse of writing the high word of the shifted data to the adjacent register of the X or Y groups of registers begins. ry signal decline

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at the output of the element And 6, again switching the shift counter 18, returns it to the initial state, which leads to the clearing of the trigger 19 of the cycle. In this case, all outputs of the control decoder 21 are set to low levels, which results in the installation of one of the triggers 22-25. When the pulse at the output of the cycle trigger is read, the next data is read from the buffer registers. If there is still information in the buffer registers, a high level is returned to the output of the And 30 element, which leads to a repetition of the read cycle — data from the buffer registers. To form the image element from the control computer, two accesses are required, one each to zone X and one to write or erase in zone Y (Fig. 2). After installing two triggers 22 and 23 or 24 and 25 at the output of the elements And 26 or 27, a high level is established, which leads to the launch of the display panel by recording (erasing) the image element. At the output of the element OR NOT 20, this sets a low level, which blocks the element AND 30 for the duration of the display board. After the display board is finished, the triggers 22–25 are cleared and a high level appears at the output of the OR-NOT element, allowing the reading from the buffer registers. The entire described process of reading from the buffer registers along with the operation of the display panel is performed in no more than 20 µs.

Claims (1)

Invention Formula A device for displaying information containing a gas-discharge indicator panel, the vertical and horizontal tires of which are connected to the outputs of the keys of the first and second groups, respectively, the information inputs of which are connected to the outputs of the registers, respectively, X and Y coordinates, recording mode and erasure trigger, first to fourth elements And, readiness trigger, device selection trigger, coordinate increment counter, shift counter, OR-NOT element, write decoder, address selector, whose information input is The first address address of the device, characterized in that, with the aim of increasing device speed, a clock pulse generator, a pulse counter, a block of permanent memory, a synchronizer register, a three-element shifter, the cycle trigger, an erase trigger on the X coordinate, an erase trigger on the Y coordinate, the first and second buffer registers are entered into it. the record decoder, the second information input of which is connected to the output of the counter of the coordinating resolution input — to the output of the second element AND, the outputs of the first and second groups of the record decoder are connected to the recording inputs of the registers respectively in the X and Y coordinates, trigger records on the X coordinate, trig. Dion inputs of which are connected to The Y coordinate write hero, key, address register whose information input is the second device address input, the address register entry input is the input of the device address record and connected to the read record of the ready trigger and device select trigger whose information input is connected to the selector the address, the control input of which is the input for setting the device address, the outputs of the ready trigger and the device select trigger are connected respectively to the first and second inputs of the seventh And element, the output of which is connected to the recording inputs of the first and second buffer registers and the key input, the output of which is the device output, the information input of the first buffer register is the information input of the device, inputs h: the shadows of the first and second buffer registers are connected to the installation input of the shift counter, input resolution of the control decoder, the first input of the second element I and with the output of the cycle trigger, the installation input of which is connected to the output of the fifth element I, the first input of which is connected to the element OR is NOT, and the second and third inputs are connected to the readout outputs of the first and second buffer registers, respectively, the write enable outputs of which are connected to the first and second inputs of the sixth And element, the output of which is connected to the ready input trigger input, the information output of the first buffer the register is connected to the information input of the shifter, the address input of which is connected to the information inputs of the count of the arrival of the coordinates and the decoder of control, with the information output of the second th buffer register and to the first data input 15 20 25 thirty 35 40 45 50 55 the output of the shifter, the setting inputs of the registers on the X and Y coordinates are connected to the reset input of the triggers of the write and erase modes, triggers to write and erase on the X coordinates and to the first output of the synchronizer register, the group outputs of which are connected to the control inputs of the keys first and the second group, and the information input of the synchronizer register is connected to the code of the constant memory block, the first, second and third-party address inputs of which are connected to the outputs of the cycle counter, the recording mode trigger and the erase mode trigger No, recording inputs of recording mode and erase trigger are connected respectively to the second and third outputs of the synchronizer register, the clock input of which is connected to the pulse input of the pulse counter and the output of the clock generator, informational inputs, recording mode and Erasable triggers are connected to the codes the third and fourth elements, respectively; nor to the first and second inputs of the OR-NOT element; the input of the control of the inversion of registers in the X coordinate is connected by the output of the third element AND, the first and second inputs of which o connected to the trigger outputs, records on the X and Y coordinates, the setup inputs of which are connected to the first and second outputs of the control decoder, the third and fourth curves of which are connected to the setup inputs of the erase trigger on the X and Y coordinates, respectively, the outputs of which are connected to the first and second inputs of the fourth element I, the outputs of the register recording resolution in the X and Y coordinates are connected to the first and second inputs of the first element I, which is connected to the second input of the second element I and to the counting input tchika -siklov. 365 O a write decoder, the second information input of which is connected to the output of the counter of the coordinate coordinates, and the enable input - to the output of the second element And, the outputs of the first and second groups of the write decoder are connected to the recording inputs of the registers respectively of X and Y, the information inputs of which are connected to the output of the shifter, the installation inputs of the registers by the X and Y coordinates are connected to the reset input of the recording and erase triggers, recording triggers and erasing on the X and Y coordinates and the first output of the synchronizer register, the outputs of which are connected to the control inputs of the first and second keys groups, and the information input of the synchronizer register is connected to the code of the permanent memory unit, the first, second and third-party address inputs of which are connected to the outputs of the cycle counter, the recording mode trigger and the trigger erase input, recording entries of recording mode and erase trigger are respectively connected to the second and third outputs of the synchronizer register, the clock input of which is connected to the pulse input of the pulse counter and to the output of the clock generator, information inputs, recording mode triggers and Erasure are connected to the encoders respectively The third and fourth elements None to the first and second inputs of the element OR NOT, the control input of the inversion of registers on the X coordinate is connected to the output of the third element AND, the first and second the inputs of which are connected to the outputs of the flip-flops, records on the X and Y coordinates, the setup inputs of which are connected to the first and second outputs of the control decoder, the third and fourth indicators of which are connected to the setup inputs of the erase triggers on the X and Y coordinates, respectively, the outputs of which are connected to the first and the second inputs of the fourth element And, the outputs of the resolution of recording registers by coordinates X and Y are connected to the first and second inputs of the first element And, the code of which is connected to the second input of the second element And and to the counting input of the counter -single. 38 L initial state (/ the second 3 / 7e / / 77