SU1241281A1 - Device for displaying information on television display screen - Google Patents

Abstract

The invention relates to automation and computing and can be used in display systems for alphanumeric and graphical information with television-type indicators. The purpose of the invention is to increase the speed of the device, which is achieved by introducing new blocks and functional relationships that allow making changes to the displayed data without affecting the entire array of displayed information and changing only that part of it that relates to the data being changed. The device contains the first and second memory blocks, the first, second and third registers, the counter, the OR element, the interpolator, the switch, the character generator, the addressing unit and the synchronizer. The operation of the device is based on the conditional splitting of the indicator block screen into square (or rectangular) areas of familiarity (G), each of which has a hard correspondence with one word address of the first memory block, and there is no tight binding of the addresses of the second memory block to the 3M screen The total number of words of the second memory block (Kc2) depends on the total number of graphics, their placement on the screen and is determined by the formula. m the number of familiarity, N - the number of raster lines in the horizontal strip ZM). The word width of the second memory block should correspond to the number of image decomposition elements (points) of graphic data on a section of the raster line within one 3M. The device implements: a mode of writing character data, which is completed by forming graphics on one raster line, and switching to another (switching to another 3M), a reading mode, which periodically reads the data, converts it, and sets it to indicator data. block, erase mode, similar to the write mode, and the difference is in the write by tri; the addresses of the first memory block are not character codes, but zeros. 5 il. with S (/)

Description

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The invention relates to automation and computing and can be used in display systems for alphanumeric and graphical information with indicators of television.

The purpose of the invention is to improve the speed of the device.

FIG. 1 shows the block diagram of the device, FIG. 2 is a unit of under-erase 5 in FIG. 3; addressing unit j in figure 4 is a synchronizer.

The device contains the first 1 and second 2 block and memory, the first 3, second 4 and third 5 registers, counter 6, the element OR 7, interpolator 8, switch 9 Signal generator 10, block 11 write-erase, block 12 addressing, synchronizer 13.

The first input 14 of the element 7 OR is connected to the output of the character generator 10,. the second input of which is connected to the output 15 of memory block 1, the second input of which is connected to the output 16 of the counter b, the output 17 of the register 3 is connected to the switch 9, the interpolator 8, the output 18 of which is connected to the block 11, the counter b and the synchronizer 13, p The 19th and 6th 20 inputs of which are connected to the interpolator 8, the 10th 21 output of the synchronizer 13 is connected to the block 12, the second 22 output of which is connected to the synchronizer, the first 23 output to the block 2 and the switch 9, the output 24 of which is connected to the block 1 whose first input 25 is connected to the synchronizer, w The output 26 of which is connected to the switch 9, the first output 27 to the register 3, the first input of which is the input 28 of the device, the fifth output 29 of the synchronizer 13 is connected to the character generator 10, the ninth output 30 and the seventh input 31 to the block 11 The output 32 of which is connected to the register 5, the output 33 of which is connected to blocks 2 and 3, the output 34 of block 2 is connected to registers 4 and 5, the output 35 of register 4 is connected to element 7 OR, the sixth output 36 of synchronizer 13 is connected to the register 4, the third output 37 with a counter 6 connected to its third input 38, the eleventh out d 39 - with the unit 2, input 40 kotoro- I-O is connected to the block 11, the seventh output 41 - a register 5, an output of OR 7 and eighth output sinhro2412812

The base 13 is the second 42 and the first 43 outputs of the device.

The write-erase unit 11 contains counters 44-46, a decoder 47 and a commutator 48, Counters 44 and 45 are reversible and are intended to count increments of ± dx and ± lu, respectively. The increments, l and l, are received from integrator 8 from output 18, and increments 10 NIN. 1y from integrator 8 through synchronizer 13 from output 30. The initial installation of counters 44 and 45 is performed by the initial data, by output from the output - 17 register 3. Counters 44-46 form the overflow and: loan signals (SP1, SP2, SPZ), which at input 31 arrive at synchronizer 13. Output signals from counter 44. arrive at the inputs of the binary deciphering 475Bb - strokes which are output 32 blocks and are connected to the inputs of the register 5,

With the help of a score of 1, a 45 is determined

25 i-fflap.niHe bits of block 2 address. Output signals with. the counter 45 through the switch arrives at the input 40 (address inputs of the lower bits) of block 2.

30 Counter 46 is intended for counting raster lines in erase modes and image data. The counter width must correspond to -; the number of raster lines in one

horizontal strip familiarity. The signals of the horizontal frequency (f) to the counter 46 are received from the ninth output 30 of the synchronizer 13. The output signal 1 from the counter 46 is fed to

Q second inputs of the switch 48, which is controlled by control signals (UPK) 5 arriving via one of the buses of the output 30 of the synchronizer 13. The overflow signal of the counter (PPE) 46 goes to the synchronizer through one of the buses of the input 31,

.

, Addressing unit 2 contains m 49., triggers 50 and 51, counter 52, .5.3 WM element, Memory 49 is intended to store single words, characterizing the use of block 2 addresses. Word count 49 is equal to familiarity in which can be placed graphic

55 business. If at any memory address 49 is recorded 1., then this means that the group of addresses of block 2, whose CJl bits are the corresponding 3

The memory address 49 contains graphic data. If the address of memory 49 contains O, then this means that the corresponding group of addresses of block 2 is free and can be used to record graphic data related to any familiarity screen. The presence of memory 49 allows for a quick search for free addresses of block 2 without access to it and thus significantly speed up the process of recording and erasing graphic data.

The search for the addresses of the memory 49 in which O is recorded is carried out as follows. On one of the buses of the tenth output 21 of the synchronizer 13, a Reset signal (CBP) is set to O, the counter 52. Then the synchronizer 13 forms a Read memory (4tn) signal on one of the output buses 21. The PTP signal repeats until until the trigger 50 does not fix the zero state of the memory address 49. The memory addresses (DAD) are acquired by the DAD signal, which is fed through one of the output buses 21 to the counter 52.

The Recording Resolution (RE) signal comes from the output of trigger 50 via one of the output buses 22 of the synchronizer 13, which stops the DAD by fixing in the counter 52 the first address of the group of free addresses of block 2.

In the counter 52, the addresses of block 2 are set, arriving at the output 15 of block 1 if there

of the decisive signal of the UAP on one of the output bus 21. In the mode of erasing graphic data, when setting the memory address 49 and the presence of a signal, the Memory Record (STD) on one of the output 21 buses in memory 49 is written O.

h.

Upon receipt of signals at the input 33 Graphic data (DG) and Resolution of the analysis of graphic data (RAGD), and also if at least one 1 is present in the graphic data, trigger 51 is triggered, forming an occupancy symptom (PZ) signal on one of the output 22 buses.

The synchronizer 13 contains a generator 54 clock pulses (GTI), divider 55 frequency ,, elements 56

5 Yu

5 0 5

about

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CJ

0

five

2814

and 57 OR and programmable logic matrix 58 (PLA).

GTI 54 is implemented according to the standard scheme and forms two sequences of pulses that are phase-shifted relative to each other, one of which from output 59 goes to divider 55. Frequency divider 55 is also implemented according to the standard scheme. Output signals from different points of the frequency divider 55 are fed to the inputs 60-63 of the PLA 58, as well as to the output 42 of the block and the device.

Elements 56 and 57 OR signals from output 15 of block 1 are received, and if there is a single signal at least in one bit, signs of the presence of sign or graphic information will be formed at their output, which are fed to inputs 64 and 65 of the PLM 58. At inputs 66- 76 PLA 58 receives signals from other units of the device. When all input signals are affected, PLA 58 at outputs 77–95 generates synchronization signals for all blocks in accordance with the device operation algorithm.

The device works as follows.

The operation of the device is based on the conditional splitting of the screen of the indicator block into square (or rectangular) areas of familiarity (G). Each ЗМ has a strict correspondence with one address of the word of the first memory block 1, which stores information about the signs and graphic elements displayed in this ЗМ. Those words of block 1, which correspond to empty 3M, contain O in all bits. In block 1, the codes of the characters displayed in the corresponding GC are stored, and the initial addresses of the groups of addresses of the block 2, which store graphic data related to this GC, are in the dotted representation (1 corresponds to the light part of the image, O - dark).

There is no hard linking of block 2 addresses to the ZM screen. The total number of words of the block 2 (Кс2) depends on the total amount of graphic data, their placement on the screen and can be determined by the formula Кс2 Кз, - N (.., where is the total number of ЗМ, containing graphic data and N is the number of raster lines in the horizontal strip of 3M. The word width of block 2 must correspond to the number of elements of the decomposition of the image (points) of the graphic data on the section of the raster line within one 3M,

Information 1 from the source of the displayed data (not shown) on the device input 28 is written to register 3 with a control signal. Write to register 3 (ZP RGZ) on one of output buses 27, which is generated in the synchronizer 13 by the write synchronization signal, coming from the data source to the synchronizer-13 on one of the input bus 28,

The bits of the information recorded in register 3, which determine the device operation mode (data recording or erasing, data: graphic or sign), are output from output 17 to the synchronizer 13 input. Depending on these signals, the synchronizer generates control and synchronization signals ensuring skinny procedures.

In the recording mode of the sign data, the synchronizer generates the signals of the Register 3 (ChTRGZ) signals on one of 1PIN of output 27, Turn on switch 9 (КВ9) on one of output buses 26, Record of memory block 1 (ЗП БП1) on one of output buses 25 and Installing counter 6 (At SCF) on one of the output bus 37, Under the influence of these signals, character codes from register 3 are recorded in block 1 through switch 9 at addresses set in counter 6. If block 1 addresses are followed, the synchronizer is at one of the output bus 37 generates signals that determine the unit changes of these a When recording graphic data, the synchronizer 13 generates a signal. Installing an interpolator 8 (UI8) on one of the output buses 20 and Installing a BZS11 (UBZS11) on one of the output buses 30. When these signals are applied, interpolator 8 inputs the initial data for forming graphs, in counter 6, the high bits of the code defining the initial 3M graphics, and the lower bits of this code are entered into block 11,

Then the synchronizer 13 on one of the output bus 25 generates the signal CTEP1, the data read from block 1 on output 15 arrives at the input of the synchronizer, which in the presence of a non-zero code of graphic information on one of the output bus 21 generates a signal UAP, and the address is entered in block 12, the low-order bits of block 2 are determined by block 11 and enter block 2 at input 40.. According to the signals of ChTPP2 and ZP WP 5, which are formed by the synchronizer 13 on

5 outputs 39 and 41, respectively, are read by e on block 2, the graphic data are recorded in register 5, then the signal on one of the output buses 20 starts, interpolator 8, increments and X from which, through block 11, are recorded in register 5 through output bus 32, the increment signal from the interpolator 8 on one of the output bus 19 first goes to screen 5 and switch 13, which stops feeding on one of the output bus 20 clock pulses to the interpolator, stopping it. Then a word of graphic information related to

0 ODB: OY raster line, with newly entered data, is read out of register 5 and returned to block 2 by the ChTRGZ command to ZPBP2 at outputs 41 and 39, respectively. Thereafter

- synchronizer 13 on one of the tires

output 30 generates a midrange signal and a change in the state of the meter

block 11. Next, the synchronizer 13 again generates the signals CHTP2, ZPRG5 and, in the absence of the output 19 on the one of the buses, a signal of the completion of the formation of graphics, starts the interpolator again, starting a new cycle of forming the graphic data on the other raster line.

If in the process of forming the graphic block 11 at the output 31 causes overflow or borrowed signals, then the synchronizer 13 corresponds to it; it changes the state of the counter

 6 signals at the output 37, which determines the transition of the formation of a graphic image into the next 3M.

. The cycle of recording graphical data on the newly installed counter

The 5 6 address begins by reading block 1 at that address.

If the graphic data is entered into a PM, in which they have previously been absent

in block 12, the search for the free address of block 2 is first carried out when the control signals CHTP and PAP are fed to it from the bus output 21 of the synchronizer 13. Recording is done after the synchronizer 13 receives the relay signal from the block 12 via one of the output buses 22. The higher bits of the address of block 2 are received over the input 23 buses through the switch 9 and on the information inputs of block 1 and are written there with the presence of the signal BP1 on one of the input 25 buses. In this case, the need to read block 2 before writing new data absent because recording is vodits by svobodnm address block 2. In the rest recording procedures similar to those described.

In the read mode, data is periodically read, converted and transferred to the indicator block. This is implemented as follows.

At one of the output 37 busses, the synchronizer 13 generates a reset signal for counter 6. Then, the signal CHTP1 on one of the input 25 buses reads the word of block 1, which is analyzed in synchronizer 13. If there is no display in this ZM, the signal from the synchronizer. 13 on one of the output bus 37, a single increment of the counter 6 is performed. In the presence of sign data in one ZM, input to the character generator is performed

10 under the influence of the control signals of the synchronizer 13 at the output

29. If there are graphic data in this ZM, the synchronizer 13 on one of the output 21 buses generates a UAP signal allowing the entry of the upper bits of the address of block 2 to block 12 on the output 15. The lower bits of the addresses of block 2 in the read mode correspond to the numbers rows in the horizontal band ZM (NT-J,) and come from the block

11 at the entrance 40.

The graphic data read from block 2 in the parallel code is output from output 34 to register 4, where, under the influence of signals from ChTRG4 on one of the 5 output buses 36, they are converted into video code, which is fed to input 35 of element 7 OR, and then output is 20

25

about

Q

-

0

five

DU 43 - to the video input of the indicator unit.

Similarly, reading, converting and transmitting information to the indicator unit for other GCs is performed. The imaging of one frame is completed when the counter 6 is input to the input 38 of the overflow signal synchronizer 13.

The procedures for erasing signed data are similar to the procedures for recording them. The difference is that the entries at the required addresses of block 1 are not character codes, but zeros.

Erasing graphic data is also much the same as recording them. The deletion is performed using the integrator 8 after the input data has been received and distributed among the units of the device. The difference is that in this case, in register 5, the graphic units are deleted, and not their addition.

Another difference between erasing and recording mode is the need to check the presence of the remainder of graphic units in this ZM after the completion of erase operations. This test is implemented as follows. After the integrator 8 is stopped by an overflow or loan signal from block 11 with the help of the counter N. In this block all the addresses of block 2 related to this SM are read. The read data is entered into the register 5, and then goes to block 12, and at the same time, block 12 is received on one of the output bus 21 of the synchronizer. The block 12.fixes the presence of at least one unit in the graphic data related to this ZM, forming a PZ signal on one of the output buses 22. When this signal appears, the analysis operations stop and the procedures for erasing the graphic data in the other ZM continue.

If there is an overflow signal of the counter N in the absence of a PZ signal, this means that the erasable graphic data in the PM was unique and now it is free. In this case, the memory of block 13 is written to zero and at the address set in the counter the address of this memory is then reset this counter, and the zero address of block 2 through switch 9 is recorded in block 1 at the address set in counter 6, completing the procedure for erasing graphic data related to this PM.

Then, the state of counter 6 is changed to 1, the synchronizer 13 switches the switch in block 11, and the graphic data operations continue until they are completed by a signal from the integrator 8 on one of the inputs 19 of the synchronizer 13, as in the recording mode.

The proposed device allows making changes to the displayed data without affecting the entire array of displayed information and changing only that part of it that relates to the data being changed.

Claims (1)

Invention Formula A device for displaying information on a television indicator screen, comprising a first block of a block, a character generator, a switch, a counter, an interpolator, first, second and third registers and a synchronizer, first, second, third, fourth, fifth, sixth seventh the outputs of which are connected respectively to the first inputs of the first register, switch, counter, first memory block, character generator, second register and third register, the first input of the synchronizer, which is the input of the device, is connected to the second input of the first the register whose output is connected to the interpolator input, the second input of the output device and the second inputs of the counter and the synchronizer, the first and second outputs of the counter are connected respectively to the third input of the synchronizer and the second input of the first memory block, the third the input of which is connected to the output of the switch and the output to the second input of the character generator and the fourth input of the synchronizer, the fifth and sixth inputs of which are connected respectively to the first and second outputs of the interpolator, the eighth output of the synchronizer is the first output of the device, characterized in that in order to improve the speed of the device, it contains a serially connected addressing unit and a second memory unit, a write-erase unit and an OR element, the inputs of which are connected to the outputs of the character generator and the second register, the second input of which is connected to the second output of the second memory block connected to the second input of the third register, the first, second and third inputs of the write-erase unit are connected respectively to the third interpolator output, the first register output and the ninth synchronizer output, first, second and the third outputs of the write-erase unit are connected to the seventh synchronizer input, the third input of the third register and the quarter input of the second block of the network, B1) the inputs of the third register are connected to the BToptiW input of the second block n and the first input of the addressing unit, the second input of which is connected to the tenth output of the synchronizer, the eleventh output of which is connected to the third input of the second memory unit, the second output of which is connected to the eighth input of the synchronizer, the second input of the addressing unit is connected to the output of the first memory block , the first output of the addressing unit is connected to the third input of the switch, the output of the OR element is the third output of the device. ( fuez T5 53 Stf 55 38 37 28 22 G5 77 II one  101Lg 737f75766 l f 77787980819283 S 78 7980 8 IL 20 21  Compiled by, Grishin Editor T. Parfenova Tehred O. Sopko Proofreader M. Yojo Order 3602/46 Circulation 455 Subscription VNIIPI State Committee GCCP for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 58 SOflfZfS 858fS7 99833091 92353135 25 2S 2123 30 3 37334f Phi. four