SU1361614A1 - Information-displaying device - Google Patents

Abstract

The invention relates to computing and m. used in information display systems. The purpose of the invention is to expand the field of application of the device. This is achieved by introducing the shift register 6, the buffer register 5, the control unit 3, the multiplexers 9 and 10, which allows changing the configuration of symbols during operation of the device. 2 hp f-ly, 5 ill. CL O5 O5

Description

The invention relates to computing and can be used in a system for displaying information on a computer.

The purpose of the invention is to expand the field of application of the device by providing the possibility of changing the configuration of symbols.

In Fig. 1 is a diagram of the device; Fig. 2 is a control block diagram; FIG. 3 is a synchronizer circuit; figure 4 is a diagram of the synchronizing pulses; FIG. 3 is a diagram of the clock pulses of the process of information exchange between the device and the computer.

The device contains the first 1 and second 2 memory blocks, the control block 3, the television indicator 4, the buffer register 5, the shift register 6, the first 7, the second 8, the third 9 and the fourth 10 multiplexers, the first 11 and the second 12 row counters and 13 characters in line.

The control unit 3 contains (FIG. 2 first 14, second 15, third 16, fourth 17, fifth 18 and sixth 19 elements AND, first 20, second 21 and third 22 NOT elements, first 23 and second 24 triggers, first counter 25 and synchronizer 26.

The synchronizer 26 (FIG. 3) contains a generator of 27 pulses, the second 28 and the third 29 counters, the seventh 30 and the eighth 31 elements I.

The device works as follows.

The device contains blocks. intended for regeneration of the image on the screen of the television indicator 4, and blocks controlling information exchange between the device and the external computer.

The process of regenerating the image on the screen of the television indicator 4 is performed as follows.

The screen of the television indicator 4 is divided into a familiarity grid. The familiarity is a matrix of 8x8 pixels. Each familiarity of the grid corresponds to a certain cell in the first memory block 1. Codes of the displayed characters are written in the cells of the first memory block 1.

According to the character codes from the second memory block 2, a dot symbol sweep is selected, in which the backlight

five

five

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five

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five

A vaema point is encoded 1, and all other points are encoded O.

In the process of forming the video signal at the input of the television indicator .4, each row of the scan matrix of the displayed symbol is sequentially recorded one after the other in shift register 6.

The row recorded in shift register 6 is pushed bit by bit onto the screen of television indicator 4, so the symbol sweep matrix fills a certain familiarity on the screen.

When the device regenerates the image on the second counter of 12 lines, the line number in the familiarity grid of the screen is formed, on the counter there are 13 characters in the row -7 the familiarity number in the line. Based on the contents of these counters, the code of the current character is selected from the first memory block 1 (the third 9 and fourth 10 multiplexers in this case are opened to pass the contents of the counters to the address inputs of the first memory block 1).

The selected character code is fed through the first multiplexer 7 to the second address input of the second memory block 2, and a character scan is selected from the last. To access the current symbol scan line on the first 11 lines from the sensor, the line address is formed, which through the second multiplexer 8 goes to the first address input of the second memory block 2. The symbol scanning line selected in this way is written into the shift register 6 and, as the beam travels, it shifts bit by bit onto the screen of the television indicator 4, forming an image. At the end of the formation of the frame image counters 11-13. the frame sync pulse arriving from the tenth output of control unit 3 is reset to 0, and with the scan of the new frame, the first memory block 1 is viewed from the O cell.

In the process of displaying information, information is exchanged between the computer and the device. At the same time, the displayed information on the screen of the television indicator 4 changes. When recording in the first block 1 of new character codes on the screen of the television indicator 4, the displayed characters change. Change

3. 13

the contents of the cells of the second memory block 2, on the screen, change the configuration of the displayed characters.

Consequently, in the process of displaying information on the screen of a television indicator 4, the first 1 and second 2 memory blocks participate in image regeneration and enter into information exchange with a computer, and they are connected to the main memory busses of the computer as additional memory blocks.

The connection of the first 1 and second 2 memory blocks to the blocks of the device for image regeneration and to the buses of the RAM memory unit (input and output buses of the device) is performed in the time division mode.

Multiplexers are used for switching the address bus of the first 1 and second 2 memory blocks during image regeneration and exchange with an external computer (multiplexers 9 and 10 for the first memory block 1, multiplexers 7 for the second memory block 2 and eight).

When the device is disconnected from the tires of the external computer (when there is no exchange of information), the output bus of the device must be disabled. For this purpose, a buffer register 5 is used, which is intended for temporary storage of information when transmitting it from the cell of the second memory block 2 to the computer.

Controls the operation of the device in the process of regeneration of the image and during the exchange of information by the device and the computer unit 3 controls.

Scanning the image on the screen of the television indicator 4, iterating over the cells of the first block of screen memory 1, forming the video signal shift at the output of register 6, recording and reading information from the first 1 and second 2 memory blocks are synchronized.

Figure 4 presents a diagram of the clock pulses of the device.

The pulse sequence a (Fig. 4) is removed from the output of the pulse generator 27 and is master for the device. Under the action of the considered sequence of pulses, the line is shifted

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matrix sweep character on the register 6 shift and write a new line.

The pulse sequence b (Fig. 4) is formed at the sixth element And 19 and is fed to the eighth output of the control unit 3. This pulse train controls the writing process of the rows of the symbol sweep matrix into shift register 6.

Writing to shift register 6 is as follows.

The pulse of the sequence b is fed to the control input of the shift register 6 and sets the record mode. In the next cycle with the arrival of the first pulse of the sequence a (in Fig. 4 it is hatched), recording is performed.

The pulse sequence is removed from the output of the first counter 25 and is fed to the output 16 of the control unit 3. Under the action of this sequence of pulses, counters 12 and 13 form the cell selection address of the first memory block 1, and on the first counter there are 11 lines — the number of the current row of the symbol sweep matrix.

In the process of displaying information on a television indicator 4, the first 1 and second 2 memory blocks participate in image regeneration and enter into information exchange with a computer. At the same time, the operation time of the first 1 and second 2 memory blocks in each case is determined by the sequence of pulses in (Fig. 4) as follows.

During the passage of a positive pulse of a sequence of pulses into the first 1 and second 2 memory blocks participate in the regeneration of the image, the result is that the scan line of the displayed symbol is recorded from the second sequence 2 memory block.

During the passage of the negative pulse of the pulse sequence in (Fig. 4), the first 1 or second 2 memory blocks are recorded or read under the control of an external computer. The information is written to one of the memories or to the buffer register 5 by a pulse of a sequence of pulses g (Fig. 4), which is formed on the fifth element 18 of the control block 3.

one

Leia, provided that the first trigger 23 is in the state l.

In the period of information exchange between the device and the computer, the information contained in the first 1 and second 2 memory blocks is updated.

The display information is updated as follows.

The first memory block 1 works with the computer only in the input mode, and the codes of the new displayed characters are recorded in the first memory block 1.

The second memory block 2 works with a computer in input and output mode, and the following operations can be carried out: introducing a sweep of new characters into free memory cells, eliminating old (unnecessary) ones, changing the configuration of the characters themselves using shift operations, OR, AND , NOT.

The connection of the first 1 and second 2 memory blocks to the input and output buses of the device when exchanging information between the device and the computer is performed as follows.

Before starting the exchange of computers, the device selects a sequence of pulses d from the address key (Fig. 5), which is formed on the element And 17 of the control unit 3. Address key

consists of a common signal. Choosing a device coming from a computer to the input of control unit 3; and Waiting for the computer (fifth input of the control unit 3). Sync pulses of the address key are represented by a sequence of pulses (figure 5).

With the arrival of the leading edge of the negative pulse of the sequence of pulses e (the same sequence of pulses is represented in FIG. 4 by sequence c), the first trigger 23 switches to state 1 according to the established address key and from that moment the information exchange between the device and the computer is allowed.

The confirmation by the device that the exchange is allowed is made by setting the ready signal (sequence of pulses and, FIG. 5) to the sixth output of the control unit 3, which is also the output of the device.

A ready signal is generated at the second trigger 24 on state 1.

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about

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the first trigger 23 with the arrival of the leading edge of the pulses (a sequence of pulses 3, FIG. 5) formed on the fifth element And 18, when set to 1 the first trigger 23.

The process of recording information in the selected cell of the first 1 or second 2 memory blocks is carried out as follows.

The cell address of one of the memory comes from the input 15 of the device to the address inputs of the first 1 and second 2 memory blocks. At the same time, the chip of multiplexer 7-10 is opened with a negative pulse. Of the sequence e (Fig. 5) to pass the address from the input 15 of the device to the address inputs of the first 1 and second 2 memory blocks.

The selection of one of the memory for recording information is carried out on the most significant bit of the address bus (input 14 5 of control unit 3).

If the most significant bit of the address bus is O, the signal value is allowed

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It has

no record, then opens the first

element and 14 and on signal resolution

1-1

records coming from input 1 /

control unit 3, pulse, records (pulse sequence h) from the output of the element And 18 passes through the open first element 14 and to the control input of the first memory block 1 and information from the device data input is recorded in the selected cell of the first memory block 1 . If the high-order bit of the address bus (memory input of the control unit 3) is 1, then the recording is made in the cell of the second memory block 2. Writing to the second block 2 of the memory of symbols is carried out similarly. In a similar way, as for the first memory block, only a write pulse is generated on the second AND 15 element, while the first And 14 element is covered with an inverse signal of the higher bit of the address bus.

In the process of recording, the data output of the device must be closed, for this it is necessary to close the buffer register 5. The transfer to the third state (closed state) of the buffer register 5 is performed as follows.

The recording signal (high level) coming from the device input to

input 17 of control unit 3 is inverted on the second element 21 and the invert recording signal (low level) locks the third element 16, which blocks the signal access. Selecting a device to the control input of buffer register 5 from input 18 of control unit 3.

The process of reading information is performed only for the second memory block 2 and is performed as follows.

The address of the computer to be exited to the device input 15 from the second memory block 2 extracts the contents of the selected cell, which is recorded by the write pulse (pulse sequence e, figure 5) generated on the fifth element 18, and entered into the buffer register 5 and the same pulse sets the second trigger 24 to state 1. By the ready signal (a sequence of pulses and, FIG. 5) set by the control unit 3 to the sixth output, the computer reads the contents of the buffer register 5. In this case, the buffer register 5 is open to pass data output device oystva

This is how the contents of the selected symbol cell are entered into the computer.

The exchange cycle between the device and the computer is completed by removing from the idle input the signal control block 3 Waiting, as a result of which the first 23 and second 24 triggers on the inputs are reset.

Claims (3)

Invention Formula 1, A device for displaying information comprising a television indicator, a first storage unit, a second storage unit, a first multiplexer, a second multiplexer, a character counter in a row, a first row counter and a second row counter, whose information input is connected to the first output of the first row counter, the information input of which is connected to the first output of the character counter in the line, and the second output of the counter, of the lines connected to the information input of the second multiplexer, the output of which is connected to the first address input second o memory block whose second address input is connected to the output of the first multiplexer, whose information input 5 0 5 0 at 0 6 0 5 It is connected to the output of the first memory block, characterized in that, in order to expand the field of application of the device by providing the possibility of changing the configuration of symbols, a shift register, a buffer register, a block, control, a third multiplexer and a fourth multiplexer are entered into it, whose information input connected to the second output of the character counter in the line; the first output of the control unit is connected to the counting inputs of the character counter in the string and the control inputs of the first, second, third and fourth multiplex The information input of the third multiplexer is connected to the output of the second counter, the rows, and the output of the third multiplexer is connected to the first address input of the first memory block, the control input of which is connected to the second output of the control unit, and the second address input of the first memory block is connected to the output the fourth multiplexer, the memory input of the control unit is the first input of the device, the address inputs of the first, second, third and fourth multiplexers are connected to the first input of the device, the information The input of the first memory block is the second input of the device, the information input of the second memory block is connected to the second input of the device, the third output of the control block is connected to the control input of the buffer register, the quarter output of the control block is connected to the read input of the buffer register, the output of the second block the memory is connected to the information inputs of the shift register and the buffer register, the output of which is the device data output, the fifth output of the control unit is connected to the control input of the second memory block, The output of the control unit is the device ready output, the seventh output of the control unit is connected to the clock input of the shift register, the eighth output of the control unit is connected to the control input of the shift register, the output of which is connected to the information input of the television display, the ninth code of the control unit with the TV indicator line scan input, the tenth output of the control unit91 It is connected to the frame indicator input of the television indicator and to the installation inputs of the second row counter, the first row counter and the character counter in the row, the recording enable input of the control unit is the third input of the device, the enable input of the control unit is the fourth input of the device, the input of the block waiting control is the fifth device input 2. The device according to claim 1, wherein the control unit comprises six AND elements, three HE elements, two triggers, a first counter and a synchronizer, the first output of which is the tenth output of the block, the second output is the ninth output of the block, and the third output is connected to the input of the first counter, the input of the first element is NOT the input of the block memory sample, the first input of the second element is AND connected to the address input of the block, the second input of the second element AND is the input of block recording resolution, the input of the second element NOT and the first first entry The first element AND is connected to the block write enable input, the output of the first element is NOT connected to the second input of the first element AND whose output is the second output of the block, the output of the fifth element AND is connected to the third inputs of the first and second elements AND, to the counting input of the first trigger and is the third output of the block, the output of the fourth element I is connected to the inputs R of the first and second triggers and to the input D of the first trigger, the first input of the fourth element I is the input of the block sampling resolution, the second input of the fourth element And is input to the sleep block, the first input of the third AND gate five 0 five 0 five 0 five 1410  connected to the sample enable input of the block, the second input of the third element AND is connected to the output of the second element NOT, and the output of the third element I is the fourth output of the block, the direct output of the first trigger is connected to the input D of the second trigger and the first input of the fifth element AND , the forward code of the second trigger is the sixth output of the block, the output of the second element AND is the fifth output of the block, the first output of the first counter is the first output of the block, the input of the third element NOT and the first input of the sixth element AND are connected to the first output One of the first counter, the second output of the first counter is connected to the second inputs of the fifth and sixth elements, and the third output of the first counter is connected to the third. the inputs of the fifth and sixth elements are And, the output of the sixth element And is the eighth output of the block, the output of the third element is NOT connected to the counting input of the first trigger and the fourth input of the fifth element And, the third output of the synchronizer is the seventh output of the block. 3. The device according to claim 2, about 10 and that the synchronizer contains a pulse generator, the second and third counters, the seventh and eighth elements And, the output of the pulse generator is connected to the input of the second counter and is the third output of the synchronizer, first, second and the third outputs of the second counter are connected to the inputs of the seventh element I, the output of which is connected to the input of the third counter and is the second output of the synchronizer; the first, second and third outputs of the third counter are connected to the inputs of the eighth element And whose output is It is the first synchronizer output. Figz LJLLLLLLPZHPGShL -P one one g: € Well I and Editor I.Nikolaychuk Compiled by A. Glotov Tehred A. Kravchuk Proofreader G. Reshetnik Order 6295/51 Circulation 433 Subscription VNIIPI USSR State Committee for inventions and discoveries 11-3035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 P l .lt one P FIG. five