SU1244656A1 - Information output device - Google Patents

Abstract

This invention relates to the field of computing. It can also be used as an output of a general-purpose computer for a specialized device in the systems of the operative communication of a person with a computer. The aim of the invention is to increase speed by reducing the editing time of the output information by shifting a part of the image down and pasting the bottom D lines to the spaced apart, which is achieved by introducing an address generation unit. 1 hp ff, 3 ill. € (L

Description

one

The invention relates to computing technology, is designed to output J1H information from a computer, and can be used in design and construction automation systems for automated data processing, in dialog systems.

The aim of the invention is to increase speed by reducing the editing time of the output information.

Fig. 1 is a block diagram of the device; Fig. 2 is a functional block diagram of the formation of addresses of memory cells; figure 3 - the location of the information on the screen.

The proposed device contains a memory block 1, a decoder 2, a pulse distributor 3, a synchronization block 4, a switch 5, a block: 6 coordinate transformations, an address generation block 7, the first counter 8, the first element 9, the second counter 10, the comparison element 11, the first register 12, the second element And 13, the element OR 14, the trigger 15, the third element And 16, the second register 17, the counter 18.

The device works as follows.

. Block 4 generates pulses corresponding to the required raster discretization; the indicators control the scanning of the latter. These pulses arrive at the distributor 3, having carried out its temporary reference to the clock signal of unit 4.

In memory block 1, each bit of the image corresponds to one bit encoding its brightness. The coordinates of the image recorded in memory block 1 form a field of mathematical coordinates of 2 points horizontally and 2 points vertically with a coordinate origin in the lower left corner.

The present invention allows the image to be moved downward on a screen, starting with the coordinate Ur on the lines. In this case, the lower D1) lines of the screen are moved to the spaced area in accordance with FIG. 3.

For this, the computer puts the value of y in the first register 12, respectively, and the value in the second register, 17. Registers 12 and 17 have inverse outputs. -Signal 20

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of the second quenching pulse coming from the synchronization unit 4 to the first input of the unit 7, sets the counters 8 and i О and the trigger 15 to the state

5 O. At the beginning of the visible stroke of the indicator frame from block 4, the second (clock) input of counter 8 receives pulses with a period equal to the duration of reading one word

 from memory block 1. Counter 8 recalculates the number of words of a block of 1 memory decreasing in one image line. Signals from the high-order output of counter 8

 through the first element And 9 arrive at the clock input of the counter 10, which performs the recalculation of the image lines. The outputs of the counter 10 are connected to the inputs of the comparison element 11, where the code of the current line is compared with the code Ur, after the inverse outputs of the first register 12. When the codes match, the comparison element-11 generates a comparison pulse, which through the second element 13 and the element OR 14 transfers the trigger 15 to the state 1 at the clock input, and also writes the initial code ay from the inverse outputs of the second register 17 to the counter 18. The counter 18 includes m binary bits. O on inv.ersnom trigger output 17 locks the first 9 and second 13

35 elements And, and 1 at the direct output of the trigger 15 connects the output of the counter 8 words to the clock input of the counter 18 through the third element 16. The counter 18 recalculates the image lines until it overflows, i.e. counts and lines. The overflow signal from the output of counter 18 through the element OR 14 transfers the trigger 15 back to the state O. Thus, the rows 10 are recalculated by the counter 10. The outputs of the counter 10 and the counter 18 form together with the outputs of the counter 8 the addresses read from memory 1 of words. At the same time, if the direct output of the trigger 15 is equal to O, then the outputs of counters 8 and 10 are connected to the memory block 1 through the switch 5, and if the direct output of the trigger 15 is 1, then the outputs of the counters 8 of the memory 1 are connected to the input 55 and 18. For this, the direct output of trigger 15 is connected to the control input of the switch.

thirty

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5. When submitting 5 word read addresses to the switch, the counts output of the 8 words form the lower address addresses, and the outputs of the 10-line counter or counter 18 make the older ones. In this way, information is read from memory 1.

The conversion of the read information into a video signal, as well as the recording of information in the memory block 1, are performed identically to the known device.

Thus, the invention makes it possible to achieve enhanced functionality by providing the possibility of rearranging fragments of the invention by shifting a part of the image down and inserting the bottom lines.

Claims (2)

1. A device for outputting information comprising a memory unit, a decoder, a pulse distributor, a synchronization unit, a switch, a coordinate conversion unit, the inputs of the first group of which are information inputs of the first group of the device, information outputs of the first group of the coordinate conversion unit are connected to the information inputs of the switch, and the information outputs of the second group are connected to the information inputs of the decoder, the outputs of which are connected to the inputs of the first group of the memory block, the outputs of the group These are the information outputs of the device, the outputs of the synchronization unit group are connected to the inputs of the first group of the pulse distributor, the outputs of the group of which are connected to the inputs of the second group of the coordinate conversion unit, the first and second outputs of the distributor of pulses These third and fourth outputs of the pulse distributor are connected to the control input of the decoder and to the first control input of the switch, respectively, the switch outputs are connected to the inputs the second group of the memory block, the inputs of the second group of the pulse distributor are the control inputs of the device, the outputs of the second group of the pulse distributor are the control outputs of the device, the first output of the synchronization block is the output 25 ..., , .five. - YU . 15 20 . 30 35 40 45 50 55 device sync signal, which is due to the fact that, in order to increase speed by reducing the editing time of the output information, an address shaping unit is entered into the device, the group outputs of which are connected to the address inputs of the switch the input of the switch, the first and second inputs of the address generation unit are connected to the second and third outputs of the synchronization unit, respectively, the inputs of the first and second groups of the address generation unit are information inputs the second group of mouth- roystva 2. The device according to claim 1, which means that the address generation unit contains three counters, three AND elements, a comparison element, two registers, an OR element, a trigger, the R inputs of the first, second counters, and a trigger. the first input of the block, the output of the most significant bit of the first counter is connected to the first inputs of the first and third elements AND,. the output of the first element I is connected to the clock input of the second counter, the outputs of which are connected to the inputs of the first group of the comparison element, the output of which is connected to the R input of the third counter and to the first input of the second element AND whose output is connected to the first input of the OR element, connected to the trigger input of the trigger, the inverse output of which is connected to the second inputs of the first and second elements And, the direct output of the trigger is connected to the second input of the third element And is the output of the block, the output of the third element a AND is connected to the clock input of the third counter, the overflow output of which is connected to the second input of the OR element, the inputs of the first register are the inputs of the first group of the block, the inverse outputs of the first register are connected to the inputs of the second group of the comparison element, the inputs of the second register are the inputs of the second group of block , the inverse outputs of the second register are connected to the inputs of the third counter group, the outputs of the remaining bits of the first counter, the outputs of the second and third counters are the outputs of the block group. T t Editor L.Povkhan Compiled by V. Bazovkin Tehred N. Bonkalo Proofreader A. Obruchar Order 3915/51 Circulation 671 Subscription VNIIG1I USSR State Committee for inventions and discoveries 113035, Moscow,, Raushsk nab., 4/5 Production and printing company, Uzhgorod, ul, Proektna, 4