SU1062766A1 - Device for displaying information onto crt screen of television receiver - Google Patents

Abstract

DEVICE FOR DISPLAYING INFORMATION ON SCREEN, TV RECEIVER, containing sequentially connected memory block, converter of binary code to television signal connected to television receiver, data input unit connected to control unit, first output of which is connected to second converter input the binary code to the television signal, the second output of the control unit — the first input of the memory unit; the AF outputs — with the inputs of the first, second, and third elements AND; the output of the first element And it is connected to the input of the first counter, the first output of which is connected to the input of the second counter, which is different in that it contains the third and fourth counters and the first and second groups of OR elements, whose inputs are connected to the outputs of the first and second and the third and fourth counters, respectively, and the outputs of the elements of the OR groups are connected to other inputs of the memory block.

Description

The invention relates to computing, namely, devices for displaying information on a cathode ray tube screen using a television method of forming symbols.

A device for displaying information using the television method of forming symbols is known. This device has a sequential access memory. Information on the screen is displayed by characters in rows from left to right and line by line from top to bottom in accordance with the sequence of writing the character code in the image regeneration memory l}

The closest technical solution to the image is a device for displaying information comprising a serially connected address counter, a memory block, a binary code converter to a television signal, a display unit and a data block connected to the control unit, the first output of which is connected to the memory block ti, and the second output - with the converter of a binary code in a television signal, and also two elements 2I-OR,. the third output of the control unit is connected to the second inputs of the first elements AND 2I-OR, the fifth output of the control unit is connected to the first input of the second element AND the first element 2I-OR, the sixth output of the control unit is connected to the second inputs of the second elements AND 2I-OR , the seventh output of the control unit is connected to the first input of the second element AND the second element 2I-OR, the output of the address counter is connected to the first input of the first element and the second element 2I-OR 2.

The device displays the characters sequentially in rows. As well as sequentially in columns in accordance with the sequence of recording information in the memory block. The address counter is made up of a string and character counter.

The row counter width is determined. I. ...;

h.Eog :,: ь;, -..- where K is the number of information lines

characters.

The character counter width is determined by

m eog, 5,

where 5 is the number of columns CHNffiOnOB

on the screen.

The sum of the character and line counters determines the address counter size: p - n + trj In the recording mode, as well as the display in rows, the counters are connected in series, with the output of the high order of the row counter

connected to the input element 2I-OR, the output of which is connected to the input of the character counter. The speed of the device in these modes is determined by the time of setting the address at the input of the memory block and is

T-X i-LI y

where q is the delay introduced by the row counter,

"- the delay introduced by the element 0tom 2I-Sh1I,

j- delay introduced by the character counter. .

In the column display mode, the counters are divided, clocked 5, and controlled separately from the control unit. The lack of address in the counter structure of the element II-OR, through which the row and character counters are connected in the recording and display mode by lines, limits the speed of the display device.

The summation of the delay time of the element 2I-OR s. The delay of the row counter leads to a shift in time (2p + 1) of the write cycle or the reading of the fronts of the high bit signal of the row counter and the lower bit of the character counter.

As the frequency increases in the Record mode and reads in rows, the divergence of the fronts leads to a false setting of the addresses at 2p + 1 clock cycle at the address input of the memory block, and the device loses its workability.

The drawback of the device is the low speed in the recording and display mode in the rows.,.

0 The purpose of the invention is to improve; Saving the device performance.

The goal is achieved by the fact that the device containing the following i. properly connected memory block

5 binary-to-converter; levizionny signal connected to; TV receiver, a data input unit connected to the unit. control whose first output

Q is connected with a second input of a binary code converter into a television signal, a second output of the control unit with the first input of the memory unit, and the other outputs with inputs

the first, second and third elements And the output of the first element And connected to the input of the first counter, the first output of which is connected to the input of the second counter, the third and fourth counters and the first and second groups of elements OR, whose inputs are connected to the outputs of the first and second and the third and fourth counters, respectively, and the outputs of the elements of the OR groups are connected to other inputs of the memory block.

FIG. 1 shows a block diagram of the device / in FIG. 2 - 4 information display modes.

The device contains an address counter 1, which includes a 2 line counter and a 3 character counter, an address counter 4, consisting of a 5 line counter and a 6 character counter, counter outputs 2 and 5 lines are connected to the inputs of the elements of OR group 7, the outputs of the counters 3 and 6 characters one by one are connected to the inputs of the elements of OR group 8, the outputs of the elements of OR groups 7, 8 are connected to the direct inputs of memory block 9, the control block 10 connected to block 9 of Pm1 and those to the inputs of elec tions AND 11 - 13, Input control unit 10 is connected to the output of data input unit 14, in The output of the memory unit 9 is connected to the binary code conversion unit 15 to the television signal 15, the second input of which is connected to the output of the control unit 10, and the output to the television receiver 16.

The device works as follows.

From the data input block 14, information is input to the control block 10, which sets the memory block 9 to the Write or Read mode, and then transmits to it information received from the data entry block 14, in addition, the control block 10 outputs control signals the first input of the element 11, which permits the Write or Display mode in rows, to the second | input of the element 11 is fed the clock {frequency of recording or reading information, the output signal of the element 11 controls the operation of the counter 1 address in the mode Write and Display in rows as well as to the inputs of elements 12, I13 for gating them in the Display by Column mode.

The second input of the I12 element is supplied with the clock read frequency of the rows, the output signal of which controls the operation of the 5 rows counter, the address counter 4, and the second input of the I13 element is fed with the clock reading frequency of the symbols that controls the counter 6 characters of the 4 address counter . The address codes of the memory cells are generated by counters 1 and 4 of c1dres, which through the elements of OR of groups 7 and 8 are fed to the inputs of memory block 9. Counters 1 and 4 addresses operate in the modes defined and clocked by control unit 10. In the Display mode, information from the output of the memory unit is fed to the input of the binary code conversion unit 15 to the television signal, from the output of which is fed to the display unit.

In the Record mode, the control unit 10 on the second output prohibits the operation of the binary code 15 conversion unit to the television signal, the first output of the control unit 10 on the memory block 9 firstly receives a control signal that transfers the memory block to the recording mode, and then information received is received by control unit 10 from input unit 14 of data. The output of the control unit 10 receives a strobe signal at the first input of the element I11, the second input of the element I11 receives the information recording clock frequency, the signal locking the elements I12, I13, the clock-frequency of reading the lines and the clock frequency of reading the characters.

Since the elements I12 and I13 are closed, the counter 4 of the address is in an idle state, the clock frequency of the recording from the output of the element I11 is fed to the input of the counter 1 of the address consisting of a sequence. tally connected counter 2 lines and counter 3. symbols. The counter 1 of the address determines the address of the recording of information in the memory block, which from the output of the elements of OR groups 7, 8, is fed to the input of the block of memory 9 and 9.

The display mode is divided into two sub-modes: Display in rows (the sequence of displaying characters on the screen in accordance with familiarity, Figures 2 and 3) and Display in columns (Figure 4). In the Line-by-line mode, the signal from the second output of the control unit 10 enables the operation of the binary code conversion unit 1 to the television signal, from the first output j and the control unit 10 a signal is transferred that transfers the memory block 9 to the Read mode, to the second input of the I11 element Receives the clock frequency of reading information. Ele: I12, I13 cops are closed, from the output; Element 11 is the read clock frequency input to the address counter 1, which determines the address of the read information from memory block 9, this address is fed through the elements of OR 8 to the address input of memory block 9 ti. The information is selected from the block. The memory 9 is located at the address 3, the address counter 1, from the memory block 9, enters the input of the binary code conversion unit 15 into a television signal, where a television signal is generated, which is fed to the input of a television receiver.

In the Display by Column mode (Fig. 3), the control unit 10 from the second output enables the operation of the block

15 converting a binary code into a television signal, a signal is sent to the first output to the input of the memory block, which brings the memory block to the Read mode, the prohibition signal is output to the second input of the element I11 and the clock frequency of the readout from the output of the control unit 10 does not pass to the output element of the AI counter 1 address is in the idle state. The first inputs of elements I12 and I13 receive a strobe signal allowing the receipt of the clock frequency of reading lines from the control unit 10 to the second, the input of element I12, from the output of which it goes to the input of the counter 5 lines.

The clock frequency of reading the characters comes from the control unit 10 to the second input of the element I13, the output of which is fed to the input of the counter 6 characters. From the outputs of the control unit 2, the address codes through the OR elements of group 7, and from the outputs of the count 5 characters 6, through the elements of OR group 8, are sent to the address inputs of the memory block 9. Information read in accordance with these addresses is sent to the information

0 is an input of a binary code to a television signal, the output of which the signal is fed to a television receiver.

Thus, the proposed device provides an increase in speed in the Record and Display modes in rows, which greatly expands the area of application of the device.

Claims (1)

DEVICE FOR DISPLAYING INFORMATION ON A SCREEN, TELEVISION OF A RECEIVER, containing a memory unit connected in series / binary, a binary code to> television signal converter connected to a television receiver, a data input unit connected to a control unit, the first output of which is connected to the second input of the converter binary code into a television signal, the second output of the control unit with the first input of the memory unit, and the “other outputs with inputs of the first, second and third AND elements, the output of the first AND element is single with the input of the first counter, the first output of which is connected to the input of the second counter, characterized in that, in order to increase the speed of the device, it contains the third and fourth counters and the first and second groups of OR elements, the inputs of which are connected to the outputs of the first and second and the third and fourth counters, respectively, and the outputs of the elements OR groups are connected to other inputs of the memory block. Ί ϊ screen in which method