SU1410091A1 - Device for vertical shift of line on display screen - Google Patents

Abstract

The invention relates to automation and computing and can be used in text displays on cathode ray tubes. The purpose of the invention is to increase the speed of the device. The device contains the first counter 1, the second counter 2, the third counter 3, the tator 4, the memory block 5, the trigger 6, the element 7, the fourth counter 8, the fifth counter 9, the adder 10 with the corresponding connections. Speed is provided to the summing 19 and subtracting 18 inputs of the signal counter 9, which change its content, which ensures that information is shifted up and down along the display screen when the trigger state 6 is zero. 3 il. with

Description

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The invention relates to automation and computing and can be used in text displays on cathode ray tubes.

The purpose of the invention is to improve the speed of the device.

Figure 1 shows the functional diagram of the proposed device, figure 2 - functional diagram of the switch, fig.Z - timing diagram of the device.

The device contains the first 1, second 2 and third 3 pulse counters, switch 4, memory block 5, trigger 6, element 7, fourth 8 and fifth fifth pulse counters, adder 10 and inputs 11-23 and outputs 24 blocks of the device

Switch 4 contains elements And 25 and elements 26 of the first and second groups, the group of elements OR 27, the element 28 and the inputs 29-31 and the outputs of the 32 elements of the switch.

Counter 1 is a binary counter with a reset circuit. The counting is performed by a difference from one to zero.

Counter 9 is a reversible binary counter with chains of parallel reception of information for setting the initial value and resetting. The counting is performed by a difference from one to zero, the recording is a high level of the recording signal.

Counter 8 is a binary counter with parallel receive information for setting the initial value and reset. The recording and the count are made by a difference from one to zero with the corresponding recording and counting signals. The counter has m + n bits. In the information reception circuits, the first level of signals will be low-level signals (zero recording), while the remaining m bits will record the contents of counter 9

Trigger 6 is an RS trigger.

Counters 2 and 3 are reversible binary counters with chains of parallel reception of information for setting the initial value and resetting.

Adder .10 is a parallel binary adder.

The device operates in edit and print modes.

The initial state, (the zero code is stored in the counter, trigger 6 is in the zero state) is set by input 17 of the initial setup.

The editing mode is characterized by the fact that trigger 6 is in the zero state. At the same time low

signal level from direct output

the trigger 6 locks the counter 9 on the record input, overwrites the contents of the counter 1 into the counter 9 and passes pulses through the element

5 and 7 to the counting input of the counter 1. The counter 8 records the contents of the counter 9 according to a signal arriving at the input 20 of the frame sync pulse. In this case, the input 22 of the record is fed

0 low signal level, the address inputs of memory block 5 through switch 4 transfer the contents of counter 8. The high signal level received at sync input 21 reads 5 information from memory block 5 at the address generated by counter 8 and the difference from units to zero the contents of counter 8 is incremented by one.

0 By applying a series of pulses over the synchronous input 21, information is read from memory block 5 and outputted to outputs 24 for display on a display (not shown).

By sending signals to summing 19 and subtracting 18 control inputs of the device, you can change the contents of counter 9 and shift the information down and up on the display screen.

Q In the lower n bits of the counters 8 corresponding to the number of characters in the line, the signal from the input of the 20th frame sync pulse records all zeros (the display starts at the beginning of the line), and in the older m bits, the contents of the counter 9.

The recording is made upon the arrival of a high level signal at the input 22 of the recording, the contents of the counters 3 and 2 (cursors of the sign and lines) are transmitted to the address inputs of block 5. According to the high level signal on the synchronous input 21, the block 5 records information from the information inputs 11 at the address generated by the counters 2 and 3,

the state of which is controlled by signals arriving at summing 15 and subtracting 16 inputs of counter 3, which

five

issues transfer signals to the counting inputs of counter 2, and then the information is recorded in the next line. Thus, information is written to all lines of memory block 5.

The print mode is set by the signal on the input 13 of the device, which sets the trigger 6 to the initial state of one. At this, the AND 7 element opens, counter 3 records the symbol address from input 23, from which recording begins, and counter 2 records the contents of the counter 1, enlarged an adder 10 to the code arriving at the input 12 and determining the screen size, and thus writing to the last line of the screen. The recording is made after the arrival of the signal at the input 22 of the recording, the address inputs of block 5 are transferred to the contents of counters 2 and 3. The signal from input 21 to block 5 records information from inputs 11 at the address generated by counters 2 and 3,

After one character is written, the contents of counter 3 (the cursor of the sign) are incremented by a signal from the summing input 15 and the recording is repeated at the new address. After the row is filled with counter 3 (the cursor of the sign), a transfer signal is output which increases the contents of counter 2 (the cursor of the row) and through element H 7 the contents of counter 1, which is transmitted via the signal from the input 20 of the frame sync pulse through counter 9 to counter 8, Thus, when reading the display, the information recorded in block 5 is displayed, starting with the address specified by the counter code 1.

When increasing the contents of counter 1, the information is shifted up, and since the contents of counter 2 (row cursor) increase in a similar way, the recording is made on the last line of the screen. In this way, the filled line is shifted up by one, releasing the space on the screen line to enter a new text line, i.e. text is displayed on the screen in a manner similar to printing text on a conventional typewriter.

The print mode is terminated with the arrival of a signal at the reset input 14, which zeroed trigger 6. Low level

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The signal from the direct output of the trigger 6 prohibits the passage of signals to the counting input of counter 1 and stops rewriting its contents through counter 9 (low signal at the recording input) to counter 8. At the same time, counter 1 maintains a state when printing, the display on the display screen is carried out, starting with the line defined by the last state of the counter 1. I

The speed of the proposed device is provided by reducing the time for switching to the print mode and depends on the frequency of the clock pulses at input 20 ..

Claims (1)

Invention Formula A device for vertically shifting lines on the display, containing four pulse counters, a switch, a memory block, a trigger and an element, whose output is connected to the counting input of the first pulse counter, the first input of the And element is connected to the forward output of the trigger, inputs Installation 1 and Installation About which, respectively, are the first and second control inputs of the device, the inverse output of the trigger is connected to the installation inputs of the second and third pulse counters, whose information outputs are connected to the information The inputs of the first switch group, the information inputs of the third pulse counter, are the information inputs of the first group of devices, the third and fourth control inputs of which are respectively the summing and subtracting inputs of the third pulse counter, the transfer output of which is subtracted the summing input of which and the second input of the element I are connected to the transfer output of the summation of the third pulse counter, the reset input of which and the reset inputs The second, first and fourth pulse counters are the reset input of the device, the first recording resolution input of which is the setup input of the fourth pulse counter, the summations of which input and the first control input of the memory block are the second recording resolution input of the device, information the input of the second group of which are the informational inputs of the memory unit, the second control input of which and the control input of the switch are the fifth control input of the device, the output of the memory unit is the output of the device, characterized in that the pulses are connected to the outputs of the first counter by a pulse, the output of the adder is connected to the information inputs of the second pulse counter, the switch outputs are connected to the address inputs of the memory unit, the input of the entry of the fifth pulse counter is connected to the forward output of the trigger, the input the device speed, it contains the reset of the fifth pulse counter; it accumulates the adder and the fifth pulse counter, whose outputs are connected to the information inputs of the fourth pulse counter, whose outputs are connected to the device reset input, the summing and subtracting inputs of the fifth pulse counter are respectively the sixth and the seventh one is controlled with information inputs of the second device inputs, informational M. M. pln "" tp 4Ti44i -n "" TTTJt / U -tJ T -n-bry rTleiTJ fTT PTGGT GTCG K OT / TIOT O swarm of switch group, information inputs of the first group of adder and information inputs of the fifth counter The inputs of the third group are the second information inputs of the adder. the pulses are connected to the outputs of the first counter by a pulse, the output of the adder is connected to the information inputs of the second pulse counter, the switch outputs are connected to the address inputs of the memory unit, the input of the entry of the fifth pulse counter is connected to the forward output of the trigger, the input the reset of the fifth pulse counter is connected to the reset input of the device, the summing and subtracting inputs of the fifth pulse counter are respectively the sixth and seventh control inputs of the device, the information TJ -n-bry rTleiTJ fTT PTHGT GTHK K OT / TIOT O The inputs of the third group are the second information inputs of the adder. J0 / 77 at oh V 29 28 G 1 31 / 77 L m-f-n 27 1 n / 77 ji J jig Reading 21 3 f P / Record Xt pZ / .J