SU1377849A1 - Data output device - Google Patents

Abstract

The invention relates to computing technology and allows displaying information on a gas discharge plasma screen (GPP) screen. The aim of the invention is to increase the speed of displaying information on the GYY screen. Information output (simple and complex characters) is carried out point by point. The change of coordinates defining the location of the element of the symbol (for

Description

(ABOUT

from 1

00

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the gigantic point on the screen, and the formation of the symbol image in the device is performed in parallel, which allows the information to be displayed on the PN screen at a rate determined by the physical features of the panel. For this, the device has a counter of 19 columns and a counter of 20 rows, allowing respectively changing the X and Y coordinates and at the same time

scan the image of a symbol that is stored in the memory block of the raster of a simple symbol or in the memory block 26 of the raster of a complex symbol, and the individual image raster of the symbol's image is scanned at multiplexer 27; 5 il.

The invention relates to automation and computing, in particular, devices for displaying information, where it can be used as a device that provides streaming display of information on an indicator screen (in particular, on a gas discharge plasma screen).

The aim of the invention is to increase the speed of information output.

Figure 1 shows the functional diagram of the proposed device; figure 2 - timing charts of his work; FIG. 3 is a functional diagram of one of the entered multiplexer units; Fig. 4 illustrates the steps of forming a symbol on a gas discharge plasma screen; 5 a, b show functional diagrams of a column counter and a row counter and the corresponding timing diagrams. I

Device for displaying information

contains block 1 of control and generation of information of microcomputer J, address decoder 2, bus data generator 3, data register 4, bus address generator 5, increment counter 6 of the first coordinate (X), increment counter 7 of the second coordinate (Y), buffer register 8 of the mode display, register 9 of the first coordinate (x), register 10 of the second coordinate (Y), register 11 of the display mode, data transfer trigger 12, AND-NOT element 13, OR element 14, two NOT elements 15 and 16, count trigger 17, the first key 18, counter 19 columns, counter 20 rows, trigger 21 prira

The first (coordinates) of the first. (X), the second 22 and the third 23 keys, element AND 24, block 25 of the memory of the raster of a simple symbol, block 26 of the memory of the raster of a complex character, multiplexer 27, element EXCLUSIVE OR 28, shift register 29, interrupt trigger 30 . The device is connected to a gas discharge plasma panel 31.

The multiplexer 27 (fig.Z) contains the decoder 32, the elements OR 33-40, the element 8 NOT-OR 41 and the element NOT 42.

The counter 19 columns (Fig.5A) contains a binary counter 43, the element is 2NE-S1I 44, the elements are NOT 45 and 46, the elements are AND-NOT 47 - 49, the element is 2NE-W-NOT-50.

The counter 20 lines (Fig.56) contains a binary counter 51, the element 2 NOT-OR 52, the element NOT 53, the element AND-NOT 54 and the element 2 NOT-OR-NOT 55.

Keys 18,22 and 23 can be performed on chips 585AP16 in the appropriate inclusion.

The device operates in two modes, which are equivalent to the two main modes of operation of the gas-discharge plasma panel 31. The first mode is the mode in which all previously output information is erased before the output of the new array of information is displayed on the screen. This mode is called the Erase mode - write. The second mode is the mode in which only one character (sign) is replaced on the screen. This

The mode is called Record mode. I

In the Erase mode - write to the information input of the decoder 2

A code is supplied from block 1, and the corresponding signal is sent to the synchronization input. Suppose that this code can be represented as a hexadecimal number D0 (hereinafter all address codes and information codes are represented as hexadecimal numbers). On the first output of the disintegrator 2 addresses

a signal appears, the polarity of which

the signal corresponds to the synchronization input of the decoder 2, This signal (the Initial Setup signal) zeroes the data register 4, the counter of 19 columns, the counter of 20 rows and the register 11 of the mode, the trigger 30 of the interrupt and the trigger 21 increments of the first coordinate (X), as well as sets to a single state the trigger of data transfer 12 and the trigger 7 of the account through the element 24. As the register 11 as a result of this operation is zero, on each of its three outputs, the rotary polarity of which corresponds to the level O. This combination of signals at the outputs of the register 11 is perceived by the gas-discharge plasma panel 31 as a command to erase all the information that is being displayed on its screen at that time. In this case, after forming the address code at the output of the address of block 1, a data code is formed on its information code, which is matched in terms of load capacity with the circuits of the device through the data bus driver 3. On the timing of the block 1, the frequency is formed so (Fig. 2, diagram a), i.e. the gas discharge of the plasma panel 31 is transferred to the Erase mode - to record, more precisely, the first stage of this mode of erasing (zeroing) the screen is performed.

Then, operations are performed to set the initial X and Y coordinates, which determine the location of the symbol (in this case, the first symbol) on the screen of the gas-discharge plasma panel 31. This is done as follows.

In the same way as described when the 8-bit code 02 is formed on the address bus, a signal is received at the third output of the address decoder 2, which arrives at the counter recording input

| Q

5 0 5 0 d

five

five

6. At this time, from the information output of the unit 1, the information code enters the information input of the counter 6 via the bus data generator 3, and this code is written to the counter. When the code D3 is received at the information input of the decoder 2, a signal is generated at its fourth output, which records the information code (Y coordinate core) into counter 7, which enters its information input via bus driver 3 data from information block 1.

After setting the initial values of the X and Y coordinates, the information display mode is set on the gas discharge plasma screen 31. Simultaneously with the setting of the panel mode (blanking or ignition of a point), the view of the displayed information, i.e. what kind of character (simple or complex character) will be displayed on the screen. Similar to that described when generating the address of an 8-bit DI code at the second output of the decoder 2, a signal is generated that records the information code sent to the information 3-bit input of the buffer register 8, the older three bits being used (D7, D6 D5) data code. Digit D6 of the information code determines the information output mode (if D6 is O, then the point is quenched, if D6 is I, then its ignition), Bit D5 determines the type of output information (if D5 is 1, then the output of a simple symbol if D5 0, then output a complex character). In this case, bit D7 is always equal to one, in order to exclude the possibility of writing into the buffer register 8 a code containing zero values for all three bits, since such a code will be perceived by the gas discharge plasma panel 31 as a command to erase all information from the screen.

As noted earlier, in the Full Fade mode or in the Erase mode — to record after the operations associated with erasing (zeroing) the entire screen, follow the steps to display the new information on the screen. AT . In this case, the D6 bit should be equal to one, i.e. ignition points. Preliminary operations completed. The first level registers contain information about the initial coordinates of the displayed symbol (counters 6 and 7) and in the buffer register 8, the type of output information (simple or complex symbol) and the output mode (quenching or ignition point) are defined

In the case of when the digit 4 is displayed on the screen of the gas-discharge plasma panel at the specified location on the screen, in the decomposition matrix 5x11 points, i.e. in the matrix is a simple symbol.

Assuming that block 1 (microcomputer), when generating information about what is displayed on the screen, uses the last DKOI code for encoding. Then the number 4 can be represented as an 8-bit code F4.

The process of forming and outputting digit 4 to the screen of the gas discharge plasma panel 3 is illustrated in FIG. 4.

From the output of the address of block 1, the decoder 2, accompanied by a control signal, receives an 8-bit code D8, which is outputted at the fifth output of the decoder 2 signal (FIG. 2, diagram b), the duration of which is determined by the duration of the control signal . Almost simultaneously with the formation of the address code at the output of the block address, the information output of block 1 forms an 8-bit code F4, which through the bus data driver 3 arrives at the information input of register 4. On the leading edge of the pulse generated at the fifth output of the decoder 2 ( Fig. 2, diagram b) writes this code to the 4 dan register, the output of which forms the 8-bit code F4, which goes to the upper bits of the address inputs of blocks 25,26 of the raster memory of simple and complex characters and will be present as long as the block I do not accept the new 8-bit code.

When the digit 4 is displayed on the screen

In the matrix of points, the second input of the sampling resolution of the block 25 from the output of the third bit of the buffer register 8 receives a signal allowing access to this block 25, the input of the high bits of the address of the block 23 from the output of the register 4 receives an 8-bit F4 code . As a result of the formation at the first output of the decoder 2 signal

about 5

0

five

The initial setting at the output of the counter 20 lines is a 4-bit code, the state of each bit of which is defined as O, which can be described by a hexadecimal number (FIG. 2, K1-K4 diagrams). This code is fed to the input of the lower-order bits. block address 25.

In Fig. 4a, the inputs and output of block 25 are designated as follows: U1 is the second input of the sampling resolution, providing access to information stored in the memory cells of this driver, if it receives a signal whose polarity corresponds to the level У2 - the first the sample enable input when a control signal arrives at which the polarity corresponds to the level O ensures the formation of the information stored in the selected memory cell; A - A3 - entry for lower address bits; A4 to A1I is the input of the higher-order address bits; B8 DS4 is the output representing five bits at which information is generated.

In FIG. 4b, diagram I illustrates both the state of the generalized address and the nbgo input of block 25, and the state of the output bits of this driver. Since the first input of block 25 so far (at this stage of consideration is) there is a potential signal, the level of which corresponds to level 1. (signal forming conditions Initial setting) j there is a potential on all five bits of the output of this driver which corresponds to level 1.

On the falling edge of the signal generated at the fifth output of the deparagator 2 (FIG. 2, diagram b), the formation and output of information to the gas discharge plasma panel 31 begins directly. On this front coming to the C input of the counting trigger 17, that at its D-input at this moment there is a level O (Fig. 2, diagram a), the account trigger 17 is transferred to the zero state, which results in the appearance at its output of a potential signal whose level corresponds to the level O (Fig. 2 diagram c). Thus, firstly, at the first entrance (input U2,

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FIG. 4a and b) of block 25 receive a signal

eight

the level of which corresponds to the level O, which leads to the reading of the selected memory cell. The state of the DS-DS4 bits of the output of block 25 in this case is shown in Figure 4b (AND diagram).

The generated code on this output

bit information entry key. 18 with the inverse output of the trigger 12 transfer data after the initial installation enters the potential O (Fig, 2, chart g). The signal generated at the output of the trigger 17 of the account, allows the passage of the clock frequency (figure 2, diagram a) through the key 18. As a result (figure 2, diagrams L - L5) to the post-io tata on the first output of the key 18 goes to the information input multi-. plexer 27 (the bits of this input in FIG. 3 are denoted by the letter B). The fourteenth code enters the address input of the multiplexer 27 (in FIG. 3 indicated by the letter A) (figure 2, diagrams e, - e 5) formed at the information output of the counter of 19 columns after the address 2 is formed at the first output of the decoder of the address. This code causes the output (indicated in FIG. 3 as E0), the formation of a signal whose level corresponds to a level is an inverse signal of this clock frequency. The state of the second output of the key 18 is determined in this case by the state of its input. The first

15 and the second outputs of this key 18 are interconnected, thereby creating an INSTALLING OR, which is characterized by the fact that if one of the signals takes the value O, then the total

20, the signal, regardless of the state of the other signals, also takes the value O. Thus, as long as the potential O is present at the second output of the switch 18, and

The nude O, which arrives at the first 25 will be such as long as the data transfer trigger 12 is in the one state, the control input of the key 22 and the counting input of the counter of 19 columns will go

30 inverse clock signals (, diagram d). The first impulse formed at the first output of the driver 18 will change the content of the counter 19 with its back front,

25 which will lead to a change in the state of its first (pin) discharge (Fig. 2, diagram). The same impulse, entering the lock input key 22, causes the formation on.

Q is its first W-pulse, the duration of which is determined by the inverse clock pulse generated on the first key of the key 18. The pulse is formed by the 1st on the first key output

g 22 arrives at the summing input

counter 6 and increases its content by one. The condition for the formation of such a pulse at the first (and not at the second) output 22 is

g of signal O on the first (and not on the second Potential signal, form ffill) information input of this key 22. This signal comes from the direct input of the element OR 33, the second input of which receives the DS0 bit, formed at the output of the block 25. Since the DS0 1 bit (diagram II in FIG. 4b), no changes occur at the output of the OR 33 element, i.e. Potential 1) remains unchanged. And since there is a potential of the same level at the outputs of the remaining OR 34-40 elements, the output of the AND-NE element 41 has a potential O, and the output of the NOT 42 element has a potential of 1. In view of the fact that the first input of the element is EXCLUSIVE OR 28 receives the potential O from the output of the second bit of the buffer register 8 (the presence of potential 1 at this output determines the point firing mode), and to its second input the signal from the output of multiplexer 27 then the output of the element EXCLUSIVE OR 28 no changes occur, i.e. as before, the potential remains O.

at the output of the trigger 17 account (figure 2,.

The diagram c) also arrives at the trigger output 21 of the increment of the control input of the key 18. Before the input coordinate (X), since when the signal is fed to this input on: the first gg of the initial settings, the signal generated on the first output of the decoder 2, entered the reset input of this trigger 21. Thus, more

and the second outputs of the key 18 presence- I111I

on what signals came to the inputs of this key 18, On the second

at initial settings were given

eight

bit information entry key. 18 with the inverse output of the trigger 12 transfer data after the initial installation enters the potential O (Fig, 2, chart g). The signal generated at the output of the trigger 17 of the counting allows the passage of the clock frequency (Fig. 2, diagram a) through the switch 18. As a result, an inverse signal of this clock frequency is formed. The state of the second output of the key 18 is determined in this case by the state of its input. The first

and the second outputs of this key 18 are interconnected, thereby creating an INSTALLATION OR, which is characterized by the fact that if one of the signals takes the value O, then the total

the signal, regardless of the state of the remaining signals, also takes the value O. Thus, until the second output of the key 18 contains the potential O, and it

at initial settings were given

conditions of the initial change of the first coordinate (X).

After changing (increasing) the content of the counter 6, the operations associated with the output of the first bit of information (the first point of the symbol) to the gas discharge plasma panel 31 are completed.

The subsequent three such steps repeat the first, i.e. do not cause ignition of points on the screen of the gas discharge plasma panel 31,

At the moment of formation of the rising rising edge of the fourth inverse clock pulse (Fig. 2, diagram e), at the first output of the switch 18, the state of the third bit of the first output of the counter 19 columns (Fig. 2, chart f) changes from level O to level 1, what causes the fifth output of the decoder 32 ((in FIG. 3, E)) to generate a signal whose level corresponds to the level O. This signal arriving at the first input of the element OR 37 causes a signal to appear at its output whose level corresponds to the level O , as at the second input of the AND element And 37 signal O is already present, coming from the output of block 25 (recall DS4 F of Fig. 36, diagram II). As a result, a signal with a level of O is formed at the output of multiplexer 27, which leads to the formation of a signal at the output of ELIMINATE SHSH 28 corresponds to level 1 (figure 2, diagram g). This signal arrives at the third input of the element IS-NOT 13, to the second input of which from the direct output of trigger 12 (after initial settings) a potential signal arrives, the level of which corresponds to level 1.

At the moment when the next clock pulse arrives (Fig. 2, the pulse marked with the letter A in diagram a), a pulse is generated at the output of the NE-IT element 13, which, arriving at the reset input of the trigger 12, translates the latter into the zero state. At the inverse output of this trigger, potential 1 is formed (FIG. 2, diagram d), which results in the appearance of level O at the second output of switch 18 (FIG. 2, diagram d), and consequently, at the control input of switch 22 and at counting at the entrance of the counter 19 columns the same level is present. Thus, the operations associated with the increment of the first coordinate (x) and the increase in the contents of the counter 19 columns are suspended from the direct output of the trigger 12 after the last transition to the zero state at the first input of the OR element 14

level O arrives. At the second input of this element, from the output of the gas-discharge plasma panel 31, the mode request signals periodically arrive (figure 2, diagram u). When the impulse marked on the diagram and the letter B, at the output of this element, arrived at the second input of the element OR 14, there was no change, because at its first input

There was level 1. Now that this level has changed with the arrival at the second input of this element of the pulse marked on the diagram and the letter C at the output of the element OR 14

a signal is generated that arrives at the information input of the register 29, to the synchronization input of which the clock pulses arrive. Dpity of impulses arriving from

the output of the gas-discharge plasma panel 31 is somewhat longer than the period of the following clock pulses, therefore the first clock pulse (figure 2, diagram a, pulse B), the back (falling) front of which coincides in time with the mode request pulse, causes the appearance of a signal which corresponds to the level of O, the output of the register 29. Signal

which is inverted by the element NOT 16, can be illustrated by the signal Transfer shown in Fig. 2 (diagram m). The leading edge of the signal

the next clock pulse (FIG. 2, diagram a, pulse E) at the synchronization input of the register 29, when its information input has a level 1, i.e. missing

signal request mode.

The leading edge of the signal Transfer arriving at the inputs of register entries 9-11, gates the recording of information arriving at information

inputs of these registers. Thus, the gas discharge plasma panel 31 receives the information & that the given values of the first and second coordinates (X and Y) need to be ignited

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the point that in figv illustrates the decomposition matrix (marked with a number).

On the back rising edge of the pulse arriving at the C input of the data transfer trigger 12 from the register output 29, the trigger 12 is again transferred to the initial (single) state, since potential 1 is present at its D input (FIG. .2 is not shown). As a result, a level O reappears at the inverse output of trigger 12 (diagram d in FIG. 2), which, in turn, contributes to the rising edge at the second output of the former 18, which resumed No interruption of the content change operation

in the first discharge, a change in the state to the opposite occurs at the output of this counter (diagram K1 in Fig. 2). The change in the output of the counter 20 leads to a change in the states at the input of the lower bits to the address of block 25 (Fig. 4b, diagram). At the output of the block 25, changes also occur (Fig. 2, L1 diagram - J15 and Fig. 4b, state diagram DS0 - DS4). Thus, with the formation of a trailing edge of a clock pulse, marked on the diagram in letter G, preparatory operations for outputting the information to the gas discharge plasma panel are carried out. counter 19 columns on e

my counter 19 (figure 2, chart e). 20 transfer output is newly formed

When this happens, the signal changes at the output of the decoder 32 (marked as E4 in FIG. 3), which contributes to the termination of the signal at the output of the EXCLUSIVE OR 28 element (FIG. 2, diagram G).

As can be seen from diagrams a and d shown in Fig. 2, the trailing edge of pulse E (diagram a) contributes to the formation of a rear free pulse arriving at the counting input of counter 19 and the control input of key 22. As a result, the output of counter 19 a signal appears, the polarity of which corresponds to the level. This signal prohibits the passage of information through the key 22 and at the same time, with its forward (rising) front, arriving at the counting input of the trigger 21, translates the latter into a single state. In this way, conditions are created, provided. The change in increment of the second coordinate (Y), which in Fig. 4b is indicated by an arrow ..-.

On the leading edge of the next clock pulse (Fig. 2a, pulse F), the counter 19 is set to the zero state of all outputs (diagrams e, - e in Fig. 2). At the same time, a short pulse is generated at the output of the transfer of counter 19 (diagram 3 in Fig. 2), which is fed to the information input of the key 23 and to the counting input of the counter of lines 20, causing an increase in the content of counter 7 by one and the contents of the counter of 20 lines also by one. Wherein

35

level O, which permits the passage of information through the key. In a similar manner, in the proposed device, forms are implemented.

25 information on each of the four marked in figure 4 points, which in the decomposition matrix are displayed on the screen of the gas discharge plasma panel 31.

In the 30th case, in the 11th row of the matrix of the 1st time, not a single point is hit, so after arriving at the counting input of the counter 19 columns of the 44th pulse, nocTynav№, ero from the first output of the key 18, the transfer output of the counter 19 is formed a short pulse (figure 2, diagram h), the eleventh in a row. This impulse causes the output of a 20-row counter to be output. A rather short impulse is also enough, the level of which corresponds to the level of O. At the same time, the output of this counter implies the status of all bits to

45. O. The impulse formed at the transfer output of the counter 20, coming through the AND 24 element to the input of the trigger setup 17 of the account, translates it into a single state, which at 5Q leads to the formation of a potential signal on the forward output 17 level 1, and this leads to the fact that the outputs of the driver 18 are closed

The 5g counting pulses of block 25. The same pulse, which is fed to the input of the installation of the interrupt trigger 30, causes the formation at its forward output of level 1, which goes to one

40

12

in the first discharge, a change in state occurs at the output of this counter (diagram K1 in Fig. 2). Change at the exit. the counter 20 leads to a change in the states at the input of the lower bits of the address of the block 25 (fig.4b, diagram W) The output of block 25 also changes (fig.2, diagram L1 —J15 and fig.4b, diagram III state DS0 - DS4). Thus, with the formation of the trailing edge of a clock pulse marked in letter A in diagram A, preparatory operations are carried out for outputting the next information to the gas discharge plasma panel. on his

five

level O, which permits the passage of information through the key 22. In a similar manner, in the proposed device,

5, the information on each of the fourteen marked in figure 4 dots, which in the decomposition matrix are displayed on the screen of the gas-discharge plasma panel 31. In the case in question, in the 11th row of the decomposition matrix 1, no single decay is found, therefore the counting input of the counter 19 columns of the 44th counting pulse, nocTynav№, ero from the first output of the key 18, a short pulse is produced at the transfer output of the counter 19 (Fig. 2), the eleventh in a row. This pulse causes the appearance at the transfer output of a counter of 20 lines to also a rather short pulse, the level of which corresponds to level O. At the same time, at the output of this counter, the state of all bits goes into state O. The pulse generated at the transfer output of counter 20, acting through the element 24 at the input of the installation of the trigger 17 of the account, translates it into a single state, which leads to the formation of a potential signal at the direct output of the trigger 17, the level of which corresponds to level 1, and this causes the closing shaper 18 outputs

g counts pulses of block 25. The same impulse arriving at the input of the installation of the interrupt trigger 30 causes the formation of a level 1 at its direct output which is fed to one

0

of the service request inputs (la figure 2 shows only one input of block 1). To this, block 1, after analyzing this request, forms a short pulse, which, after entering the synchronization input of the trigger 30 for the interrupt, transfers the trigger to the initial zero state. With this, all operations associated with the formation and output of information on a single symbol are completed. The devices for generating information are again ready to receive new information intended for display on the screen of the gas discharge plasma panel 31.

The operation mode of the proposed device (and the gas-discharge plasma panel as well) is considered when the information output (meaning the information array parameter, rather than a single character, although in the limit the array can consist of one character) its zeroing (erasing the previously displayed information). In this case, it is necessary to form impulses 18 44 at the output of the shaper. If we talk about the second mode (about speech: nme, when individual characters (characters) are replaced on the screen, then at the first output of this driver, 88 counting pulses must be received, and after extracting the first 44 pulses, the microev 1 must replace information the buffer register 8 in the part of the state change at its second output to the opposite, and in counters 6, 7 - to set again the initial values of the coordinates defining the location of the decomposition matrix of the output symbol on the screen of the gas discharge plasma panel 31. The remaining 44 impulses are formed in the same way as the preceding ones. In this mode, the following happens on the screen: In the decomposition matrix, which is called familiarity, the new symbol (this is the first stage) superimposes on the previously entered symbol (sign), and then point by point erasure of the previously entered character (sign). As a result, only a new symbol is displayed on the screen.

Claims (1)

Invention Formula A device for outputting information, a control unit and generating information, an address decoder, an information input and a synchronization input of which are connected to the output. the address and the output strobe of recording the address of the control unit and generating information, respectively, a data register, whose information input is connected to the information output of the control unit and generating information, a buffer register of the display mode and a register of the display mode, the information input and output of which are connected to the output of the buffer register of the display mode and with the output of setting the device indication mode, respectively, increment counters of the first and second coordinates, registers of the first and second coordinates, information nye inputs and outputs are connected to the outputs of counters incrementing first and second coordinate values and the outputs of the first and second coordinate data inputs respectively device increments the counters of the first and second coordinate informatsionnym.vyhodom connected to the control unit and generating Infor-; In this case, the first output of the address decoder is connected to the inputs of the O data register and the display mode register; respectively, an AND-NOT element, the first input of which is connected to the clock output of the control and information generation unit, the data transfer trigger, the reset input and the direct output of which are connected to the output The second and the second input of the NAND element, two NOT elements, the fifth output of the address decoder is connected to the data register record input, characterized in that, in order to pick up speed, the OR element, the account trigger, three keys, the column counter are entered into it lines j trigger the increment of the first coordinate, the element AND, the memory block of the raster of a simple character, the memory block of the raster of the complex character, the multiplexer, the element EXCLUSIVE OR, shift register and interrupt trigger the output and the reset input of which ELEVATED to the interrupt input and to the reset output of the interrupt of the control unit and information generation, respectively, the first output of the address decoder is connected to the input of the interrupt trigger installation and the reset inputs of the increment of the first coordinate of the column counter whose information output is connected to the address input of the multiplexer, the bits of the information input of which is connected) to the bits of the outputs of the memory blocks of the raster of simple and complex characters, information outputs of the data register and the row counter are connected to the inputs of the upper and lower digits of the address of the memory blocks of the raster of simple and complex characters, the first sampling resolution inputs of which are connected to the output of the counting trigger and to the control input of the first key, the first and second bits of the information input of which connected to the clock output of the control unit and the formation of information and with the inverse output of the data transfer trigger, respectively, the lessons of the first and second bits of the first key are combined via the INSTALL OR element and connected to the counting input of the counter of columns and to the control input of the second key, the first and second bits of the information input and output of which are connected to the forward and inverse outputs of the trigger of the increment of the first coordinate and to the summing and subtracting inputs of the counter of the increment of the first coordinate, respectively the sixth through ninth outputs of the address decoder are connected to the summation and subtractive inputs of the increment counters of the first and second coordinates, respectively, the output of the sign of the type of the character of the buffer register press display. connected to the inputs of the installation of the recalculation coefficient of the column counter and the row counter to the second input of the resolution of the memory block selection , You J5 20 25 jQ Q. With 0 A simple symbol raster and, through the first element, NOT to the second input of the sampling memory block sample resolution, the output of the quench sign discharge flag of the buffer register of the indication mode is connected to the first input of the URUNE OR, the second input and output are connected to the output of the multiplexer and with the third input of the NAND element, the transfer output of the column counter is connected to the lock input of the second key and to the counting input of the trigger of the increment of the first coordinate, the output of the transfer gate of the column counter is connected to the account The input of the row counter and to the information input of the third key, the output of which is connected to the summing input of the increment counter of the second coordinate, the transfer output of the row counter is connected to the control input of the third key, to the synchronization trigger input of the trigger and to the first input of the And element whose output is connected to the installation of the account trigger, the synchronization input of which is connected to the fifth output of the address deshator, the output of the control unit and information generation is connected to the information input of the trigger account and the input of the synchronization register of the shift, the serial information input of which is connected to the output of the OR element, the first and second inputs of which are connected to the output of the data transfer trigger and the input of the device mode request respectively, the output of the shift register connected to the synchronization input of the data transfer trigger and through the second element NOT to the recording entries of the first and second coordinates registers and the display mode register, the first output of the address decoder is connected to the data transfer trigger setup input and to the second th input AND gate, data inputs of the data transfer trigger and trigger an interrupt inputs are connected to the device 1 and O, respectively, ASHPLT: GLSH1Sh1SHYYi . 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