SU1476524A1 - Character graphic display unit - Google Patents

Abstract

The invention relates to automation and computing and can be used as an output of an information control system for displaying visual information. The purpose of the invention is to increase the speed of the device. This goal is achieved by the fact that in the device containing the gas discharge display panel, the address blocks in the X and Y coordinates, the first and second write-erase pulse generators, the first and second supporting voltage generators, the clock generator, counters, the first and second blocks fixed memory, interface block, RS-trigger, first and second elements NOT, first and second elements AND, element 2И-OR, entered a decoder, encoder, third, fourth and fifth elements AND, D-trigger, which allows em speed up the output of non-ignitable segments when encoding characters in the form of directional segments and, consequently, increase speed. 1 hp f-ly, 4 ill.

Description

The invention relates to automation and computing and can be used as an output of an information management system for displaying visual information.

The purpose of the invention is to increase the speed of the device.

The invention uses a method of encoding characters in the form of directional segments in conjunction with a dual-frequency synchronizer. Their relationship causes an increase.

the device's speed by shortening the time of the sign output and preparing the coordinates of the next sign, since the encoding of the state of the output segments controls the two-frequency synchronizer and allows output of the non-ignition segments (run mode) with a higher frequency than the ignited ones.

The essence of the invention is that two synchronizing frequencies are used for synchronization of the proposed device. One of

they coincide with the frequency of the display panel (SR sync pulses); the other frequency is much higher (also TI pulses). These frequencies, passed through the fourth and fifth AND elements, are fed to the inputs of element 2И-OR, which performs the function of a demultiplexer. The displayed sign is encoded in the form of an aggregate of ignited and non-ignitable segments. The state code of the segment (0-ignited, 1-ignited) arrives at element 2И-OR, and depending on the state code of the segment, either the clock pulses or the clock pulses are sent to the first counter. They also come in through the second block And to the second decoder. The pulses from the output of the second decoder are encrypted and fed to the first and second registers, which perform the storage and counting functions. Thus, in the first and second registers, the current coordinates transmitted to the address blots are changed. The coordinate increment is performed with the frequency of the clock pulses, if at the given moment the lit segment is output, or with a clock frequency that is higher than the frequency of the clock pulses, if the segment is not ignited. The use of the two-frequency method of synchronization allows to reduce the time for the derivation of the sign and the preparation of the coordinates of the next enaka in the line.

Figs 1 and 2 are a block diagram of a device for displaying the sign of a graphic information; ka fig. 3 time diagrams of device operation; FIG. 4 is an example of encoding a character 7,

The device contains an interfacing unit 1, an encoder 2, a 3S decoder, the first permanent memory unit 4, the first element is NOT 5, the third is 6, the first 7 and the second is 8 And, D-flip-flop 9, -RS-flip-flop 10, second element 11, element 2I-OR 12, fourth 13 and fifth fifth elements AND, first counter 15, oscillator 16 Clock pulses, second counter 17, first 18 and second 19 write-erase pulse generators, second permanent memory unit 20, first 21 and second 22 voltage-supported generators, address blocks 23 and 24 respectively

Q Q 5 5

0

50

0

there are X and Y and a gas discharge indicator panel 25.

The interface unit consists of a decoder 26 and the first 27, second 28 and third 29 counters.

The device works as follows.

The binary code of the address is fed to the information input of the decoder 26 of the interface 1 block from the information source. At the same time, a synchronizing pulse arrives at the control input of the decoder. An impulse appears at one of the outputs of the decoder 26, depending on the incoming code. If the address of the initial coordinate X is set, then the pulse from the first output of the decoder 26 is fed to the control input of the parallel register of the register 27. This pulse records the binary code of the X coordinate from the data bus to the counter 27.

In the next call of the information source, the Y coordinate code is written from the data bus to the counter 28. The write to the counter 28 is effected by a pulse coming from the second output of the decoder 4.

After the X and Y coordinates are written to the appropriate registers, a sign can be displayed on the indicator panel1. Moreover, the coordinates stored in the counters 27 and 28 determine the lower left corner of the familiarity.

Consider the output of a mark in a specific example, the character encoding (or graphic information) is stored in the first block 4 of the permanent memory. The sign is represented by a collection of directional segments. Each segment is encoded with an eight bit word. Three bits serve to encode a segment direction. Four bits encode the number of points in the segment. One bit indicates the state of the segment points (lit or extinguished). An example of encoding the sign 7 is shown in FIG. four,

The withdrawal of the sign is as follows. The decoder 26 receives the address of the counter 29, the control input of the decoder 26 receives a synchronizing pulse. The pulse from the third output of the decoder 4 is fed to the control input of the counter 29 and records the address of the displayed character in the counter 29. The twelve-digit code from the output of the counter

29

enters the input of the first block 4

permanent memory. From the block. 4, the first eight-bit word is read.

The pulse from the third output of the decoder 26 also goes to the C input of the D-flip-flop 9. Logic unit is recorded from the D-input to the flip-flop 9 and from it to the inputs of the fourth and fifth elements And 13 and 14 and the sync pulses and clock pulses are allowed to pass the inputs of element 2I-OR 12.

Signal4c output D-flip-flop 9 is fed to the output of the device and signals the unavailability of the device to exchange with the source of information. The clock pulses are generated by a generator of 16 clock pulses, and the clock pulses are received from the first output of the second block 20 of the permanent memory of the time diagram.

The pulse from the third output of the decoder 26 also goes to the first counter 15 and records the code of the number of points in the directional segment from the third output of memory 4 directly to the counter 15. The code for direction of the segment from the first output of memory 4 is fed to the input of the decoder 3. In total, it is possible to encode 8 directions of segments (Fig „4). Depending on the direction code, a pulse appears at one of the outputs of the decoder 3. The second output of memory block 4 transmits information about the state of the segment points (lit or extinguished). From the second output of memory block 4, the logical zero is sent to the elements I 1t and 12. This oz

and from the output of element 2I-OR 12 on to the counter. 15 receive clock pulses. The same pulses, passed through the element And 7, perform gating of the decoder 3. The pulses from the output of the decoder 3 arrive at the input of the encoder 2. Depending on the direction of the segment from the outputs of the encoder 2, the pulses arrive at the inputs of counters 27 and 28 and to the subtracting inputs of the counters. In this case, the code of the segment 010 (Fig, 4). With such a code, only an increment of the Y coordinate code is carried out, so that an impulse arises

ten

15

20

25

50

45 read from

4765246

at the third output of the encoder 2 and arrives at the second input of the counter 28. The code of the Y coordinate is increased. The increment of the coordinate occurs until the contents of the counter 15 becomes zero and the reverse transfer signal appears. In this case, the number of pulses is 6. The reverse transfer from the counter 15 output, having passed the NOT 5 element, allows the clock to pass through the AND 8 element from the first input to its output connected to the second input of the counter 29, the contents of the counter 29 are increased by one, and The code from the output of the counter 29 is fed to the input of the memory block 4, from which the second eight-bit word is read. Next, the device operates in a similar way, except that a unit enters from the second output of memory block 4, which permits the passage of clock pulses through element 2I-OR 12 to the first input of counter 15 and through element 7 to the first input of decoder 3. The increment of coordinates occurs with the clock frequency, which, in turn, is determined by the properties of the gas discharge display panel and does not exceed 50 kHz. The operation of the device is repeated until all code patterns of the displayed character have been read. In addition, a segment is coded that prepares the coordinates of the next character in the line. When displaying characters in a string, the control CVM (or other source of information) specifies the coordinates of the first character. The coordinates of the following characters are formed by the device itself. After all code combinations of the displayed character

memory unit 4, the last combination is decrypted by element 6. The logical unit from the output of element 6 is fed to the R input of the trigger 9. The trigger 9 is zeroed. Zero level with trigger output 9

enters the first inputs of the elements And 13 and 14 and blocks the passage of clock and sync pulses. Device operation stops. The zero level from the output of the trigger 9 also enters the output of the device and signals to the source of information about the readiness of the device to display visual information.

thirty

35:

40

55

The process of incrementing the coordinates in counters 27 and 28 during the derivation of a sign is considered. The outputs of the counters 27 and 28 are connected to the third inputs of the address blocks 23 and 24, which sample the rows and columns of the indicator panel 25 in accordance with the received binary code. The first inputs of the address blocks 23 and 24 receive control pulses from the outputs of the formers 18 and 19 of the write-erase pulses. The inputs of the formers 18 and 19 receive either ignition pulses or erase pulses, as shown in FIG. 3. These pulses travel from the second output of memory block 20. The outputs of the memory block 20 receive control pulses (Fig. 3) at the inputs of the supporting voltage generators 21 and 22, the outputs of which are connected to the inputs of the address blocks 23 and 24. FIG. Figure 3 shows the timing diagrams generated by the memory unit 20 in the ignition, purge, Erase mode. An example of coding a block of memory for the ignition mode is given. The output of the generator 16 is connected to the input of the second counter 17. The twin code from the output of the counter is fed to the first input of the memory block 20. At the outputs of the memory block 20, pulses are formed (Fig. 3) in accordance with the coding. If a logical zero arrives at the second input of the memory block 20 from the second output of the memory block 4, this means that the coded segment is not lit, and the memory block 20 forms a timing diagram of the run (FIG. 3). The arrival of a logical unit at the second input of the memory block 20 means the ignition of each point of the segment displayed on the display panel, therefore, an ignition diagram is formed (FIG. 3). In the ignition and run modes, a logical zero is present at the third input of the memory unit 20, which comes from the output of the trigger 10, the trigger 10 is zeroed after each character is output. The nulling signal comes from element 6. If it is necessary to erase the character, the source of information transmits the address code through the address bus to the decoder 26. The binary code is decrypted. At the output, a pulse appears that goes to the input of trigger 10 and sets it to

0

five

0

1. The logical unit from the output of the trigger 10 is fed to the third input of the memory block 20. The memory unit forms the erase diagram (FIG. 3). Preliminary from the source of information come the codes of the coordinates of the sign that must be erased. These codes are stored in the counters 27 and 28. Then, the transfer to the counter-29 occurs in the same way as described and an erase character encoded in the same way as the other characters is read from the memory block 4. The erasure of the mark is similar to the recording, except that the erase pulse has a different location relative to the support pulses than the ignition pulse (Fig. 3),

The table shows timing diagrams generated by memory block 20, depending on the input states.

Claims (1)

Invention Formula 1, A device for displaying enacographic information containing the first and second generators of the supporting voltage, the outputs of which are connected to the first control inputs of the address blocks, respectively, by X and Y coordinates, the second control inputs of which are connected to the outputs of the first and second write drivers, respectively erase, and the outputs, respectively, with horizontal and vertical tires of the gas discharge display panel, interface block, information, address and first control inputs They are expensive inputs of the device, a clock generator, two blocks of permanent memory, an RC trigger, two NOT elements, a 2I-OR element, two counters, two AND elements, so that, in order to increase the speed of the device, into it There are three elements And, a decoder, a D-trigger, an encoder whose outputs are connected to the second, third, fourth and fifth control inputs of the interface block, the first, second and third information outputs of which are connected to the information inputs of the address blocks, respectively, in X coordinates and Y and the first block of permanent memory, the first output of which is connected to the information input of the decoder, the control input of which is connected to the output of the first element AND, the first input of which is connected to the input of the first element NOT and from the output The first counter, and the second input - with the first input of the second element AND, with the clock input of the first counter and with the output of element 2И-OR, the second input of the second element AND connected to the output of the first element NOT, and the output connected to the sixth control input of the interface unit , the second and third outputs of the first memory block are connected to the first and second inputs of the third element I, the output of which is connected to the R inputs of the flip-flops, the clock input of the D-flip-flop is connected to the first control output of the interface block and to the control input parallel recording the first counter, the setup input of which is connected to the third output of the first block of permanent memory, the D input of the D-flip-flop is connected to the bus of a single logical potential, and the output is the output of the device and connected to the first inputs of the fourth and fifth elements And , the second input of the fifth element I is connected to the output of the clock generator and to the input of the second counter, the output of which is connected to the first address input of the second block of permanent memory, the second and third address inputs of which are connected respectively to the second output of the first block of nonvolatile memory and the exit RS-flip-flop, the S-input of which is connected to the second control output of the interface unit, the first output of the second memory block is connected to the second input of the fourth And element, the second output - to the inputs of the first and second write-erase pulse drivers, third, fourth, fifth and sixth exits The second block of permanent memory is connected to the first and second inputs of the first and second generators of the supporting voltage, respectively the outputs of the fourth and fifth elements And are connected to the first and second inputs of the element 2И-OR, the third input of which is connected to the second output of the first block of permanent memory and to the input of the second element NOT, the output of which is connected to the fourth input of the element 2И-OR. 2, the device according to claim 1, characterized in that the block mates contains a decoder and three counters, the installation inputs of which are the information input of the interface block, and the outputs of the first, second and third counters are the first, second and third information outputs of the block, respectively, the control inputs of the parallel recording of the first, second and third counters are connected respectively with the first, second and third the decoder outputs, the third, fourth outputs of which are the first and second control outputs of the block, respectively, and the information and control inputs of the decoder Rattor are respectively the address and first control inputs of the block, the summing and subtracting inputs of the first and second counters are the second, respectively the third, fourth and fifth control inputs of the block, the clock input of the third counter is the sixth control input of the block. a7 010 W I .001 100 FIG A 000 111