SU1182531A1 - Interface - Google Patents

Description

The invention relates to digital computing and can be used to pair display devices alphanumeric information that is derived from digital 5

computer, and display system, and is an improvement of the known device auth. St. No. 1129603.

The aim of the invention is to expand the class of tasks by carrying out the output of information from several displays to several boards in an arbitrary order.

Figure 1 shows the structural diagram 15 of the device *, figure 2 is a structural diagram of the display system; FIG. 3 is a functional diagram of a pulse distributor, ’in FIG. 4 a functional diagram of an exchange unit $ in FIG. 5 and 6 are functional diagrams of a switching unit and an output switching unit; 7 is a timing diagram of the passage of signals through the interface ^ 5 interface displays with a group device; on Fig - timing diagram of the device when receiving information from the display; in Fig. 9, a time diagram of the operation of the device when displaying information on the scoreboard.

The device contains (Fig.1) block 1 amplifiers, switching unit 2, address setting unit 3, shift register 4.35 distributor 5 pulses, first counter 6, permanent memory unit 7, first decoder 8, first comparison unit 9, operational memory unit 10 , second and third counters 11 and 12.40 exchange block 13, second comparison block 14, switching output block 15, group output amplifiers 16, bus 17 information inputs of the serial interface, control 45 device input 18, bus 19 inputs and outputs of the parallel interface devices.

The display system (FIG. 2) contains a group control device 20, displays 21, an interface device 22, a board 23, an input / output interface bus 24.

Distributor 5 pulses (fig.Z)

'consists of an integrating element 55

25, the counter 26, the decoder 27, the element And 28, the generator 29 of a single pulse, the trigger 30 and 31, the element And 32, the decoder 33 and the trigger 34.

The exchange unit 13 (FIG. 4) contains triggers 35-37, a decoder 38, an AND 39 element and a driver 40 of signals.

The switching unit 2 (FIG. 5) contains the address decoder 41 and the AND-OR elements 42. The switching output unit 15 (FIG. 6) contains the address decoder 43, the I-44 elements and the node group 47 of the AND blocks 45 and 46.

Consider the interface of the scoreboard, which has a parallel printing interface (for example, the Videoton-342 display), with a display system (for example, EC7906) that has a serial interface between the EC7566 group device and the EC7O66 display.

Bus 17 serial interface consists of the following set:

TIR-U type of information transmitted from the group device 20 to the displays 21 ·, SI-identifier (sync series), determining the availability of information on the TIR-U bus.

Tires 19 parallel print interface display "Videoton-342" consist of the following set:

The IF is a sign of the presence of information in the display for printing ’,

UPG print device ready;

DD data is reliable on information tires;

IP information accepted;

NA-new line, the presence of a signal. on the bus indicates that the transfer of the line from the display to print is completed ’,

D1-D7-information tires.

The display system (FIG. 2) has several displays (screen consoles) 21 (for example, EC7066) connected to several group control devices 20 (for example, EC7566).

In the group device 20 there is a local memory that stores information displayed on the screen of the displays 21 connected to it (the frequency of regeneration of information on the screen 50 times per second).

Information from different displays is transmitted byte-by-serial code via bus 17 in time-sharing mode with a frequency of 2 MHz.

Information on the computer comes in

group device 20 via bus

3 1

24 of the I / O interface and is recorded in the area of local RAM attached to this display 21. Interface device 22 listens to the information on buses 17 and 'own area of local RAM in group device 20 does not have.

In accordance with the address set on unit 3, which is identical to the address of display 21, device 22 removes information relating to a specific display from tires 17 and displays it on a given display.

Below are explanations of the algorithm of interaction of displays 21 with a group device 20. For simplicity, the number of displays 21 connected to one line of buses 17 is conventionally taken equal to four.

In accordance with the timing diagram (Fig. 7), information is transmitted from the group device 20 to the displays 21 via the interface 17 by a sequential code line by line. In this case, the information signs displayed on the screens of the displays are transmitted on the forward course of the line, and the service codes controlling the movement of the beam on the screen, on the reverse course of the row.

To control the course of the beam, three seven-bit service codes are used:

NOHS-beginning of the return stroke line, in this combination, the beam begins to move to the beginning of the new line,

COX-end of the return stroke line, for this combination, the beam returns to the beginning of a new line,

NOHK-the beginning of the reverse frame, for this combination, the beam returns to the beginning of the first line of the frame.

The distribution of time intervals is rigidly defined by the group device 20. Transmission of one frame of information from the group device

20 includes A lines, moreover. In the penultimate time interval on the return stroke of line A, the series of SI synch pulses is interrupted. This is perceived by the displays.

21 as a reset pulse to the initial state of display circuit elements. For one time interval, consisting of 36 SI pulses, the transmission ^is carried out ^{- of} one sign of information in the time division mode ί

531 4

There are 17 displays connected to this interface.

The first nine SI pulses gate the information on P1IN-U, related to the first display 21, the second nine pulses to the second display 2, and so on.

Information on the TIR-U begins to arrive at the fifth synch pulse SI, counted from the trailing edge of the reset pulse.

The device works as follows.

To display the information, the operator must preset on the transmitter 3 the code of the address of the display 21, from which the previously viewed and edited information should be displayed, and the code of the address of the board to which this information is displayed. The display address consists of high order bits, identifying the number of the tire line 17, and low bits, identifying the number of the display 21 in the line. The address of the board is set on the setter 3 in the parallel code and identifies the board number 23.

Senior bits of the address code of the display, coming from setter 3 to the input of decoder 41 of block 2, excites one of its output buses and opens AND-OR 42 elements. One AND-OR 42 element transmits the TIR-U signal of the selected bus 17 to the input of the shift register 4 and the other element AND-OR 42 is the signal of the same bus 17 to the input of the distributor 5.

When the device is powered on, the trigger 34 of the distributor 5 is set to zero. The integrating element 25 selects From the series of SI synchro-pulses arriving at its input, a reset pulse, which reset the counter 26, the shift register 4, the counter 6, the register elements of the memory block 10, · counter 11, as well as triggers 30 and 31. The zero signal from the output of trigger 34 sets the counter 12 to zero and disables its recalculation, and in block 13 resets the triggers 3537. The device is in the initial state '.

More device to implement

the output on the scoreboard should receive an impulse "Output" from the operator through the control input 18 of the device.

five

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When a signal arrives at the input 18, the generator 29 generates a pulse with a duration of at least 20 ms (the duration of the transmission of a frame of information from the group device 20 to the display 21). The signal from the output of the integrating element 25 is triggered trigger 34 and the signal from its output allows the recalculation of the counter 12 and the triggering of the triggers 35-37. Next, the device is sequentially in one even frame | The regeneration of information on the display screen takes one line to the device, and in the second odd frame, the output ¹ shows this line on the display. This feature of the device due to the need to coordinate the speed of receiving information from the bus 17 and output information through the bus 19 on the scoreboard 23.

Receiving a line of information from the tires 17 is carried out in the device in the following sequence (Fig.8). When the first SI pulse after a reset pulse arrives, counter 26 begins to count nine pulses. The code from the output of the counter 26 is decoded by the decoder 27, which produces at its outputs the signals of the ninth, third, fourth and fifth cycles. The signal of the fifth clock cycle triggers 31, allowing, in all clock cycles except the third and fourth, the SI pulses to pass through the AND 28 element to the synchronization input of the shift register 4. Information 1RIN-U comes from the output of block 2 to the information input of register 4. For seven clock cycles register 4 forms the sign code. In the two subsequent cycles, the information in register 4 does not shift. The signal of the ninth clock cycle from the output of the decoder 27 counts the counter 6. Having counted to nine, the counter 26 is triggered and the count of the next nine pulses resumes. When comparing the contents of the counter 6 with the value of the low-order bits of the address of the setting device 3, the block 9 determines information related to the specified display, and issues a signal allowing the flow of information to the block 10 and the decoder 8.

In the first time interval after the reset pulse, the group device 20 transmits a COHS code to the displays. The code adopted by register 4 is recognized by the decoder 8, On

the second output of the decoder 8 generates a signal for triggering the trigger 30 of the distributor 5. The signal from the output of the trigger 30 allows the fourth clock signal from the output of the decoder 27 to pass through the element 32 to the input of the block 10 as a signal of inversion. The zero state of the low-order counter

12, the input-read-input of block 10 determines the write mode in block 10. The seven-digit character code generated in the · internal code of the display system from the register 4 output enters the input of block 7, where it is used as the address of the cell in which the corresponding code is written mark on the scoreboard 23.

From block 7, the sign code after the transcoding arrives at the information input of block 10 and, if there are enabling signals at the inputs "Recording Resolution", the control and "Appeal" is written into the next memory cell. The write enable signal in block 1Ό is issued by block 14 when comparing the state of the counter 11 with the value of the high bits of the counter 12, i.e. in each new even frame the corresponding next line is transmitted. > __

The process of writing the character codes of the string in block 10 is terminated with the arrival of the service code of the NOHS.

According to the NOHS code, the decoder 8 generates at its first output a signal that resets the trigger 30 and simultaneously counts the unit 11 to plus one unit. Block 14 receives a comparison signal from its output and prohibits writing signs of subsequent lines of the frame into block 10.

Upon receipt from the register 4 service code NOHK at the output of the decoder 8, a signal is generated, which is recalculated to plus one counter 12.

The device enters the display mode information on the scoreboard (Fig.9).

The unit low-order value of the counter 12, which enters the read-write input of block 10, determines the reading mode. The signal from the output of the lower category of the counter 12 is cocked trigger 35 block exchange

13. Through the driver 40, the IF signal from the output of the trigger 35 is issued

7

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in block 15 and further to the corresponding block 16 amplifiers for transmission via bus 19 on the display 23. Block 15 switches all signals between blocks 13 and 16 in accordance with the address of the display 23, coming from the setter 3. The address code of the display 23 from the setting unit 3 goes to input decoder AZ and excites one of its output tires corresponding to this address. The signal from the excited bus of the decoder 43 opens the elements AND-OR 44 and AND 45, 46 of the corresponding node 47. The first element AND-OR 44 skips the signal of the FGM and the second element AND-OR 44 - the signal of the IP from block 16 to block 13, the elements AND 45 and 46 of the corresponding node 47 switch signals DC, K, HC, D1-D7 from block 13 to the corresponding block 16.

The signal from the IF board begins to perceive the signals on the tires 19. In response to the IF signal, the board sends a signal to the IP line, which, passing through blocks 16 and 15, in block 13 resets the triggers 36 and 37. Then the UGG signal comes from the board.23, which, after passing the chain of bus 19, blocks 16 and 15, cocks the trigger 36 in block 13 and reads the code of the first character of the string from the first address of block 10. The block 10 reports the completion of the read cycle with a “Data ready” signal, which triggers trigger 37, and information on the data buses of block 10 via generator 40, element 46, block 16 is output to buses D1-D7 accompanied by a signal DD passing through the trigger 37, element 45, block 16. The reception of the data sign of the board 23 is signaled by the signal PI, which is through the circuit of block 16, the second AND-OR element 44 clears triggers 36 and 37 in block 13, after which the board 23 issues a request for the next data sign by the signal Ugg Next, the data character reading cycles are repeated, and the information is read from the consecutive addresses of block 10. After reading the last character in the string (block 10’s address counter contains a number one less than the last digit in the character string), the decoder 38 generates a signal at its output that blocks the trigger 37 for all values of the address counter of the block 10 large boundary value, and at the second output - the signal that is present at the output of the decoder 38 when the value of the address counter of block 10 is equal to the boundary plus unit initsa.

When requesting a data sign with a number equal to the boundary plus one, AND 39 transmits the “Data ready” signal from block 10 to the HC line of block 13 and then through AND 45 and block 16 to tires 19.

Having received the NA signal, the board 23 removes all the signals from the buses 19. and switches to the display mode of the information received from the device.

At the end of the internal processes, the board 23 again places on the line of the UPG a signal to request information characters of the next line.

When the next NOHK code arrives from tires 17, counter 12 is recalculated and the reception of characters for the next line of frames from group device 20 is resumed, and upon completion of receiving the line, it is output on the display 23. Next, the information output frames on the display and the information reception frames from the display alternate until the counter reaches ί2 values 2Α ^Ψ 1. this value code in the counter 12, the decoder 33 outputs a signal which resets flip-flop 34. The zero value trigger 34 resets the counter 12 and the flip-flops 35-37 unit 13. The apparatus is returned to its original state set and 'ready for the next operation on the output signal from the operator input 18.

Thus, the device provides information on several displays on several boards.

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Time interval for the transmission of codes

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Time Inerter - Time interval for the transfer of the ball transfer to the latter-day

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Straight line stroke

Imposty guards counting the address counter 6 from the clock allocator 5

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The signal from the output of the lower category of the frame counter 12 to ROM 7,

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The signal from the comparison circuit FIA RAM

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Circulation signals

to RAM 7 for recording the characters of the line from the distribution “I,

clock divider 5 ---- ^ν ” ^{4 μ}

The output signal of the lower time series of the frame counter 12 to block a

Line Lj of interface 19 from block 13 through mock 15 to block 19 __

YaP interface line 19 from block 16 via block 1 $ to block 13

Line UGinterface 19 * from the scoreboard 23 to the blocks 16 (blocks 15,13)

Line D% of interface 19 from block 13 through 15 (16) to tabla 23

Pinia NA interface 19 from block 13 through blocks 15 (76) to the board 23

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Signal to access the RAM for reading the characters of the line from block 13

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Claims (1)

DEVICE FOR PAIRING on author.St. No. 1129603, which is based on the fact that, in order to expand the class of tasks of the device, a group of amplifier blocks and an output switching unit are introduced into it, and the control input the output switching unit is connected to the third output of the address setting device; the information input is connected to the Print, Data, New line and Data authenticated outputs of the exchange unit, the inputs'. connected to the information output of the output switching unit, the group of information inputs and outputs of which are connected to the groups of information inputs and outputs of the parallel interface of the device through the corresponding blocks of output amplifiers of the group. Phi *.} 5TS 1182531 one 1182531 2