SU1425772A1 - Indicating device - Google Patents

Abstract

The invention relates to automatics and computing technology and can be used in digital display devices on gas discharge display panels. The purpose of the invention is to improve the quality of the display of information due to the blanking of non-significant zeros in the higher bits. The device containing the memory block 1, the first character generator 2, the clock pulse generator 7, the counters 8, 9, the decoder 4, the key blocks 3 for the X coordinate, the key blocks 5 for the Y coordinate, the gas discharge display panel 6, the second character generator 10 is entered , the block is comparable AND, trigger 12, shift register 13, demultiplexer 15 and group of elements AND 14, this ensures that the display panel is turned on at the time of the first significant digit or the zero indication in the lower order at zero input signal, thereby increasing quality selection information and cost effectiveness of the device. I il (L

Description

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The invention relates to automation and computing and can be used in digital information display devices.

The purpose of the invention is to improve the quality of display of information due to the quenching of non-significant zeros in the old | Shih bits.

I The drawing shows the functional diagram of the device. The device contains a block of 1 block, the first character generator 2, the first block of keys 3, the decoder 4, the second block of keys 5, the gas discharge indicator panel 6, the generator of 7 clock pulses. the first 8 and second 9 counters, the second character generator 10, the comparison block 11, the trigger 12, the shift register 13, the elements 14 and the demultiplexer 15.

The device works as follows;

I The data on each familiarity is j with the hardware on the information input of the device in memory block 1 and is stored in it for the entire indication cycle I. During the recording of data in block 1 I memory at the control input; there is a level of logical 1 that holds trigger 12 and; the shift register 13 is in the initial, well-: left state. At the direct output of the trigger 12 there is a logic level O, nocTi / feeds to the control input of the decoder 4, information input I of the demultiplexer 15. As a result, the outputs of the decoder 4 and the first key block 3 control voltages , providing indication of rows of gas-discharge indicator panel (indicator) 6, are absent. In addition, at the outputs of the demultiplexer 15 and, respectively, at the outputs of the group of elements And 14 there are logic levels O, the second block of keys 5 is in the closed state and there are no control voltages providing indication of the columns. Thus, during the recording of information in the memory unit 1, the indicator 6 is not excited.

Before starting the indication of the number stored in the memory block, it is analyzed for the presence of non-significant zeros. Counters 8 and 9 are set to their original zero state.

level, and at the control input of the device a level of logic O appears.

0

5 About Q 5 Q

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enabling the trigger 12 and the shift register 13. In this case, the counter 8 addresses the first cell of the memory 1, the corresponding high-order indicator 6, and the counter 9. strobes the first character generator 2 so that its output appears the top line corresponding to the most significant bit of the indicator 6. This data is fed to the second input of the comparator block 11. The first input of the comparison unit 1 receives data from the output of the second character generator 10, which, like the first character generator 2, is counted for 4I-IKOM 8. The second character generator 1 contains seven 5-bit code combinations that form the digit O. Therefore, the first the input of unit 11 of the comparison, in this case, the data is received, which form the first row of the digit O.

The first clock pulse coming from generator 7 to the counting input of counter 9 transfers the latter to the next state. At the same time, at the output of the first character generator 2, the data of the second line of the higher digit of the indicator are input, and at the output of the second character generator 10, the data forming the second line of the digit O, and so on. After the seventh clock pulse at the output of the first character generator 2, the data of the lower line of the senior digit of the indicator appears, and at the output of the second character generator 10, the data forming the lower line of the digit O.

When the eighth clock pulse arrives at the counting input of the counter 9, it enters the zero state. At the overflow output of the indicated pulse counter, a signal arises, under the action of which the first counter 8 passes to the next state and addresses the second cell of memory 1, corresponding to the second highest order indicator of indicator 6. Similarly, the counter 9 goes through seven states and gates the first character generator 2 so that, at its output, the data from the first to the seventh rows of the second digit of the indicator appear sequentially. In this case, the output of the second character generator 10 again, sequentially and synchronously with the first character generator 2, the data of the lines appear, form

dich figure o. In the same way, data from character generators 2 and 10 is read for other bits of the indicator 6. Counter 8 has as many states as the number of bits of the indicator 6.

If the displayed number contains insignificant zeros, the data provided by the first character generator 2 and corresponding to the high bit of indicator 6 coincide with the data generated by the second character generator 10. As a result, during the first seven cycles of the display cycle at the output At block 11 of comparison, a logical level O is present, indicating the equality of the code combinations arriving at its inputs. In this case, the trigger 12 does not change its state and at its inverse output continues to be a logic level 1 that allows the data of the shift register 13 to be recorded. After seven cycles, the signal that occurs at the overflow output of the counter 8 enters the clock input of the shift register and c. its most significant bit is written to logical 1, and the logical inverse level appears at the corresponding inverse output. Shift register 13 operates so that if there is a data recording enable signal at the first control input, then its bits from the highest one, are sequentially filled with logical I as the pulses from the overflow output of counter 9 arrive at its second control input.

Consequently, if in the second most significant bit of the indicator 6 the figure O is to be displayed, the comparison block 11 fixes the equality of the code combinations, arriving synchronously from the character generators 2 and 10 to its inputs. The trigger 12 again does not change its state and with the arrival of the next pulse from the overflow output of the second counter 9 to the clock input of the shift register 13 in the first two most significant bits of the latter, logical e 1 is written, and its corresponding outputs contain logic

A. Similarly, the device detects the presence of non-significant zeros in other higher bits of the indicator 6.

72

If in the next discharge of indicator 6 a digit other than zero (the first significant digit) is to be indicated, the first character generator 2 enters data that differs from that generated by the second character generator 10 and until the moment of the appearance of a pulse at the overflow output of counter 9, the block Comparison 1 fixes the inequality of code combinations, as a result of which a logic level 1 appears at its output, which translates trigger 12 into a single state.

From this point in time, the analysis of the number of insignificant zeros is stopped and it is directly indicated on indicator 6, starting with the second significant digit.

In this case, at the inverse output of the trigger 12, a logical O signal appears, prohibiting the recording of information in the shift register 13 (with a further impact of pulses on its clock input it does not change its state). The logical signal from the direct output of the trigger 12 is fed to the information input of the de-multiplexer 15, and also enables the gate decoder 4 and, accordingly, the first key block 3, at the gate input,

Counter 9 gates the first character generator 2 and decoder 4 so that the code combination of the first row first appears, participating in the digit display, and accordingly the control voltage on the first output of the first group of keys, then the code combination of the second row of the same digit and control voltage at the second output of the first group of keys, etc.

From the output of the counter 8 to the control input of the demultiplexer 15 a binary code is received, which determines the appearance of the logical I signal at one of its outputs. Moreover, synchronization is carried out so that if data from the first character generator 2 is output to indicate a digit, for example, in the first digit of indicator 6, a logical 1 signal appears. The first output of the demultiplexer 15 and through the corresponding TS1-w element group of AND 14 (if at its input associated with the shift register there is a logic level 1) it goes to the control input of the key 5 Corresponding to the first digit of the indicator. For the second bit of indicator 6, a logical I signal appears at the second output of the demultiplexer 15, etc.

I If the induced number contains 1 insignificant zeros, then at the outputs of the shift register 13 corresponding to those of the indicator 6, for which the levels must be induced well, logical O || levels are found:

the first input of the character generator, whose address input is connected to the information output of the second counter and the information input of the decoder, the outputs of which are connected to the inputs of the key block according to the Y coordinate, the outputs of which are connected to the horizontal buses of the gas discharge display panel, the vertical buses of which are connected to the outputs of the key blocks via the X coordinate, the clock pulse generator, of which it is necessary so that

JJIOB from the outputs of the demux type of the lexora 15 is a combination of the quality of the display of information due to the suppression of insignificant zeros in the higher bits.

Without the corresponding elements of the N and the control inputs of the keys 5. In this

If the latter remain closed, the entire display cycle and the corresponding indicator bits do not light up.

Thus, at the beginning of the Injection cycle, an analysis is made of the number of pa the presence of insignificant zeros in the higher bits when the indicator is off, 4 then from the moment the bit 1 indicator is determined, which corresponds to the first starting digit of the number, the indicator turns on and non-r | proxy indication of significant numbers of a given number.

If the displayed number consists of the short codes of some zeros (O number), then in Ese the bits of the shift register 13 enter the logical 1. The levels of the logical O are present in the output, and the signals from the outputs of the demultiplexer 15 that are present at its outputs to the control inputs; all keys, except the last one, which is directly connected with the last output of the demultiplexer 15. In this case, the low-order bit of the indicator 6 is displayed

O, and all other bits

gogasheny.

Claims (1)

Invention Formula A display device containing a memory block, whose information input is the information 1G input device, the address input is connected to the output of the first counter, and the second character generator, comparison block, trigger, shift resistor are inputted to it. , the demultiplexer and the elements And, the outputs of which are connected to the corresponding control inputs of the key blocks on the X coordinate, except the last, the control input of which is connected to the output of the lower order of the demultiplexer, the other outputs which are connected to the first inputs of the elements And, the second inputs of which are connected to the outputs of the shift register, the installation input of which is connected to the installation input of the trigger and is the control input of the device, the first control is connected to the inverse output of the trigger, the direct output of which is connected to the control inputs of the decoder and the demultiplexer, the trigger input of the trigger is connected to the output of the comparison unit, the first information input of which is connected to the output of the first character generator torus and in place for information input key blocks along the coordinate X, and the second information The 45th input is connected to the output of the second character generator, the input of which is connected to the information output of the second counter, the input of which is connected to the output of the clock pulse generator50 and the overflow output is connected to the BTOpbiM control input of the shift register and the counting input of the first counter, the output of which is connected to the control input of the demultiplexer VNIIPI Order 4778/52 Random polygons pr-tie, Uzhgorod, st. Project, 4 information quality due to the quenching of non-significant zeros in higher order bits. A second character generator, a comparison unit, a trigger, a shift resistor, a demultiplexer, and And elements, whose outputs are connected to the corresponding control inputs of the key blocks along the X coordinate, except the last, whose control input is connected to the demultiplexer low-end output, the other outputs are entered into it. which are connected to the first inputs of the elements And, the second inputs of which are connected to the outputs of the shift register, the installation input of which is connected to the installation input of the trigger and is a control input The device, the first control of the shift register is connected to the inverse output of the trigger, the direct output of which is connected to the control inputs of the decoder and the demultiplexer, the clock input of the trigger is connected to the output of the comparison unit, the first information input of which is connected to the output of the first character generator and to the information input - by the inputs of the key blocks along the X coordinate, and the second information the input is connected to the output of the second character generator, whose input is connected to the information output of the second counter, whose input is connected to the output of the clock pulse generator and the overflow output is connected to the BTOpbiM control input of the shift register and the counting input of the first counter, the output of which is connected to the control input of the demultiplexer. Circulation 459 Subscription