SU1336097A1 - Information representation device - Google Patents

Abstract

The invention relates to graphic information display devices and is intended to reproduce graphic information on a gas discharge display panel. The purpose of the invention is to simplify the device. This goal is achieved by the fact that a device for displaying information containing information walks 1, w h. sync time 2, control wake 3, memory 4, pulse generator 5, element OR 6, first driver 7, the second driver 8, the counter I, the second block 13 of the keys, the gas-discharge display panel 14, the first b, 15 15k, 1 unit and depilator 16, additionally the first and second registers 9 and 10, the block of adding elements modulo two 12. You The memory block inputs are connected to the information inputs of the first register, the cat direct outputs Oogo connected to the information inputs of the second register. The outputs of the latter are connected to the inputs of the first group of the block of addition elements modulo two, the outputs of which are connected to the inputs of the first group of the second key block. This makes it possible to obtain continuous graphs of time diagrams on the gas discharge indicator screen and several channels. 1 pl. S (L with so O5 o; o

Description

The invention relates to graphic information display devices and is intended to reproduce graphic information on a gas discharge display panel, in particular, time charts for changing logic levels in digital signal processing devices.

The purpose of the invention is to simplify the device.

The drawing shows a block diagram of the device.

The device contains information inputs 1, synchronization input 2, control input 3, memory block 4, pulse generator 5, element OR 6, first 7 and second 8 pulse shapers, first 9 n second 10 registers, counter 11, block 12 adding elements modulo two, a second key block 13, a gas discharge display panel 14, a first key block 15, and a decoder 16.

The device works as follows.

In the mode of displaying information on control input 3, the signal level is high. From the output of the generator 5 pulses through the element OR 6 to the counting input of the counter 11 receives the sweep pulses. Codes coming from the output of the counter 11 to the input of the de- chirator 16 provide for the selection of vertical tires by the gas discharge indicator panel 14. At the same time, these codes are sent to the address inputs of the memory block 4 and are read out from its information cells in parallel across all channels. The address counter 11 is triggered by the sweep pulse decay, and the data is recorded in the second register 10 from the output of the first register 9. They represent the current levels of the logic levels on the current channel in the current scan inare. By the same decay of the sweep pulses, the second shaper 8 of the pulses is started, which is used to form a single pulse, the decay of which fixes the logical level values for the current sweep slot in the first register 9. The inputs of the first group of block 12 of the addition elements modulo two are supplied with the values of the logic levels through the channels on the current channel, and to the inputs of the second group - at the subsequent C are.

The horizontal tires of the gas discharge display panel 14 are divided into four groups. The keys of the first group of the second key block 13 control the horizontal panes of the panel 14 allocated for displaying low logic levels across the channels. They are excited if a logical zero level appears at the corresponding inverse output of the first register 9. The keys of the second group control the horizontal panes of the panel 14

allotted to display high logic levels by channel. They are excited when they appear at the corresponding direct output of the first level 9 register.

logical unit. The keys of the third group control the horizontal tires of the panel 14, retracted to display the transition fronts of the logic levels.

To change the information in the memory block 4, the input control 3 serves

 a low signal level that prohibits the generation of sweep pulses by the generator 5 and the first driver 7 of pulses that triggers a single pulse and triggers the counting clock 11. Then, information information 1 is successively fed through information channels 1, each value of which is accompanied by a pulse on the input synchronization, the front of which captures the next value of the input information in

0 through the memory block 4, and the decay through the OR 6 element affects the counting input of the counter 11, the gate input of the second register 10 and the input of the second driver 8 pulses.

The proposed device allows to obtain continuous graphs of time diagrams of operation of digital signal processing devices on several channels, while providing a reliable indication of the elements of the gas discharge display panel.

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Claims (1)

Invention Formula A device for displaying information containing a serially connected counter, a decoder and a first block of keys connected to the vertical sections of the gas discharge display panel, the horizontal bars of which are connected to the outputs of the second key block, the pulse generator, the OR element, the first and second pulse shapers, and the memory block , 0 informational inputs of which are informational inputs of the device, characterized in that, in order to simplify the device, it contains the first and second registers, a block of addition elements modulo two, the outputs of which are connected to the inputs of the first group of the second key block, the inputs of the second group of which are connected with inverse outputs of the first register, the direct outputs of which are connected to the information inputs of the second register, 0 by the inputs of the third group of the second key block and the inputs of the first group of the block of modulo-two elements, the inputs of the second group of which are connected to the outputs of the second register, the gating input of which is connected to the output of the element 5 OR, the address inputs of the memory unit are connected to the counter outputs, the output of the pulse generator is connected to the first input of the OR element, the output of which is connected five 2 13360974 with the counting input of the counter and the input of the one-way connected to the input of the zeroing counter, pulse generator, the output of the pulse generator and the first pulse generator are connected to the input of the gating of the transducer pulses are controllable register, information inputs to the device input, the second input element the second is connected to the outputs of the memory block, 5 OR, and the input gate of the memory block the output of the first pulse generator is the device sync input.