SU1675935A1 - Gas-discharged data display panel - Google Patents

Abstract

The invention relates to automation and computing and can be used in information display systems on gas discharge panels. The aim of the invention is to simplify the device and increase its speed, which is achieved by introducing a device containing control block 8, memory blocks 6 and 7, shift register 1, data register 10, keys of the first 2 and second 4 groups, panel 3. block 5 row selector, switch 12, register of 11 commands, block 9 synchronization. This ensures the implementation of the line-by-line recording algorithm and random access to the lines of the gas discharge panel. 2 Il.

Description

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The invention relates to automation and computer technology and is intended for use in information display devices on a gas discharge display panel.

The purpose of the invention is to simplify the device and improve speed.

FIG. 1 shows a functional diagram of a device for displaying information on a gas discharge display panel; in fig. 2 - functional block diagram synchronization.

The device contains a shift register 1 (Fig. 1), keys of the first group 2, a gas-discharge display panel 3, keys of the second group 4, block 5 of line selection, block 6 of the RAM, block 7 of the permanent memory, block 8 of control, block 9 synchronization, data register 10, command register 11, switch 12. Synchronization unit 9 contains an AND 13 element, a counter for three 14, an IS-15 element, 15 a ban trigger 16.

The device works as follows.

On the information I / O of control unit 8 (microprocessor 1806BM2) a sign code is set. The control unit 8 processes the display program. The address of the decomposition array of this sign is formed by shifting the sign code by three bits to the left and adding to it the base address of the decomposition array of the ALF alphabet located in block 7 of the permanent memory.

The sign matrix has a dimension of 6 7. In each of the seven lines there are five bits and one bit of space between the characters.

The address of the character decomposition array is written to the array of the on-screen line and the character string is displayed on the GUI. In this case, the control unit 8 provides information of the current screen line, the codes of addresses of the character decomposition arrays of which are located in the screen line array of the main memory unit 6. The first byte of the decomposition array of the first character of the string is output to the address of data register 10, for example, 177572.

The data register 10 is made on a six-bit register. The data write signal, decoded in instruction register 11, records the six bits of the character decomposition in data register 10.

GUI electrodes have pins on four sides of the panel and are combined into loops of 128 pins each (even and odd). Thus, the first 2 and second 4 groups of keys are in turn divided into

even and odd groups of 128 bits, respectively, and the shift register 1 consists of even and odd parts of 128 bits. The information from data register 10 goes to switch 12, where it is converted into two three-bit sequences, even and odd. The switch switching control of switch 12 is controlled by signals

0 arriving from the first and second output of the synchronization unit 9.

Issuing information to data register 10 is a byte transfer command with an indirect register.

5 with the addressing method, which is performed in four round-trips to the trunk. Thus, between the cycles of accessing the trunk, in which information is recorded in the data register 10,

0, there are three cycles of accessing the line, which are read cycles. From the read signal, after the arrival of the data recording signal, in block 9 of the synchronization signals are generated that control the recording of information in the shift register 1.

The data recording signal is received from the second input of the synchronization unit 9 to the reset input of the inhibition trigger 16, thereby giving permission for the signal to pass

0 reads from the first input of the synchronization unit 9 to the counting input of the counter by three 14 and removes the signal from the input to set the Counter to three 14. On the trailing edge of the third reading signal, this signal coincides with the second counter discharge by three 14) trigger 16 of the prohibition. Thus, the counter is set to three in 14 and the read signals to the counter's input are forbidden to go to three in 14.

0 Three read pulses from the clock output 9 synchronization are fed to the write input of the 1 shift register. On these pulses, three bits of even and odd information coming from switch 12 are written to the shift register 1. Thus, the first bytes of decomposing the characters of the on-screen line are written to the shift register 1.

Then, the control unit 8 issues at the address of the register of 11 commands, for example 177570, the code of the address of the current line of the screen.

The recording signal allocated on the decoder of the command register at 177570 from the output of the recording of the address of the register string 11

5 commands are fed to the control input of the block 5 line selection.

Line selection block 5 is an eight-bit address string register, and two 128-bit line decoders. The address code of the string located at

the information inputs / outputs of the control unit 8, according to the signal of recording the address of the string, is written into the register of the address of the string, decrypted and fed to one of the 256 inputs of the keys of the second group A.

In the selected row of the gas discharge indicator panel 3, the cells are lit, to which correspond the bits of the shift register 1 containing the information.

Thus, the recording of the displayed information in the shift register 1 is performed against the background of reading the character decomposition codes of the persistent memory unit 7.

The use of the proposed device in comparison with the known one allows to simplify the device as well as to increase the speed.

The known device contains an additional information buffer in the form of a RAM block, which provides for a double process of writing the graphic mark of the sign, first into the second RAM block, and then rewriting into the first RAM block, moreover, changing any element of the screen is done by display the entire amount of information on the screen. Using the proposed device for displaying information on a gas discharge display panel reduces hardware and time costs. A constructional algorithm for issuing character decomposition codes divides the time for issuing a string into two periods — issuing codes and preparing an array of an on-screen string containing addresses of the decomposition codes, for issuing the next byte of decomposition of a string of characters.

The string is displayed in six intervals, each of which consists of 32 cycles of 1.25 1 SG6 duration. For the selected row, the previous information is erased at the beginning during five intervals, then the new information is recorded during two intervals. Thus, the line is issued for a time equal to 32 x 6x x1.25 µs, and the line itself is written over a time of 32 x 2 x 1.25-1 (

ISS.

Preparing an array of the screen line to issue the next line of decomposition

represents 42 incrementing commands, which for processor 1806ВМ2 is 42 x 2, μs.

Thus, the line is displayed during preparation for changing the information in the shift register, which eliminates the need for an intermediate buffer, time for filling it and simplifies the management of information output on the GUI and provides random access to the gas discharge display panel lines.

Claims (1)

Apparatus of the Invention A device for displaying information on a gas-discharge display panel comprising a shift register whose outputs are connected to the inputs of keys of the first group, the outputs of which are connected to vertical tires of the gas-discharge display panel, horizontal tires of which are connected to the outputs of keys of the second group whose inputs are connected to the outputs of the sampling unit row, data register, control unit, control and The address informational inputs-outputs of which are, respectively, the control and address informational inputs-outputs of the device and are connected respectively to the control and address informational inputs-outputs of the RAM, to the address and control inputs of the fixed memory block and with the control and information inputs of the data register, which is so that, in order to simplify the device and increase its speed, a switch, a command register, a synchronization unit, a launch input are entered into it orogo connected to a control input the data register and with the output of the register of commands, and the clock input is connected to the corresponding output of the control unit, the first output of the synchronization unit is connected to the clock input of the shift register, and the second and third outputs are with the address inputs of the switch, the outputs of which are connected to the information inputs of the shift register, and the information inputs are connected to the output of the data register, the information input of the row selector is connected to the information input-output of the control unit, and the control input is to the output register of commands.