SU1478246A1 - Cathode-ray tube data display - Google Patents

Abstract

The invention relates to automation and computing and can be used to display graphical information from a computer. OBJECTIVE OF THE INVENTION - IMPROVE THE DEVELOPMENT OF THE DEVICE. The apparatus comprises a 1 SYNC, the first 2 and the second 3 multiplexer BLOCK 4 RAM FIRST 5 and the second 6 CONTROL UNITS, conditioners 7 VIDEO, REGISTER 8, BLOCK 9 CONJUGATION, the first 10 and the second 11 meter, backplane 12, with corresponding connections . THE DEVICE PROVIDES MAPPING, RECORDING AND ERASING THE IMAGE. MODE display unit 1 CLOCK TELEVISION generates clock and read address block of cells 4 memory, which through the first multiplexer 2 applied to its address inputs. WHEN RECORDING INFORMATION, BLOCK 9 CONFIGURATION TOGETHER WITH FIRST 5 AND SECOND 6 CONTROL UNITS FORM A POINT RECORDING CYCLE BY WHICH THE COLOR CODE COMPONENTS ARE UNDER CURRENT CHAPTER COLOR CHIVEL COLOR CODE CHAPTER COLOR COMPONENTS BELOW YOU ARE THE CHAPTER CURRENT CHAPTER COLOR CHARACTER. WITH AIRWAY CENTER. 1 IL.

Description

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multiplexers, main memory unit 4, first 5 and second 6 control units, video signal generator 7, register 8, interface block 9, first 10 and second 11 counters, internal trunk 12 with corresponding connections. The device provides display, recording and erasing of the image. In the display mode, the synchronization unit 1 generates television clock pulses and cell reading addresses of the memory unit 4, which through the first multi-. plexor 2 is sent to its address

entrance. When recording information, the interface unit 9, together with the first 5 and second 6 control units, forms a cycle for recording a point, according to which the codes of the color components are entered into the corresponding cell of the memory unit 4. When erasing the image, register 8 is zoned, and the second control unit 6 generates recording pulses with a duration of one frame interval and through the second multiplexer 3 connects the write addresses from the outputs of counters 10 and 11 to memory block 4, which results in its clearing. 1 il.

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The invention relates to automation and computing and can be used to display graphical information from a computer.

The purpose of the invention is to increase the speed of the device.

The drawing shows a functional block diagram of the device.

The device contains a synchronization unit 1, the first 2 and second 3 multiplexers, the RAM unit 4, the first 5 and second 6 control blocks, the video signal generator 7, the register 8, the conjugation block 9, the first 10 and second 11 address counters, the internal highway 12 .

The device works as follows.

In the course of work, the implementation of three modes is provided: read and write information in block 4 and screen erase mode.

Synchronization unit 1 generates horizontal and vertical sync signals that control the CRT beam sweeps (not shown). In addition, it generates a sequence of binary codes of information reading addresses, which, passing through the first multiplexer 2, the internal highway 12, arrive at the address input of block 4. At the same time, the binary representation of the image is read from the corresponding memory cells and fed to the video imager 7, where converted to

serial code of video signals of dot colors, which provides display of color information on the screen.

In the mode of recording information to the memory block 4, the command Accept command is sent to the interface block 9 via the address input of the device to the interface 9. At the same time, the color code and the number of the memory page are written to the information input, which are written to the register 8. After this, the command Za receives the address input of the device, through which the interface block 9, in accordance with the information supplied to the information input of the device, generates pulses add, subtract or reset the first 10 and

0 second 11 write address counters. At the same time, the interface unit 9 outputs control signals to the second control unit 6, which generates a timing diagram of the recording cycle and switches the first and second multiplexers so that the write addresses from the outputs of counters 10 and 11 through the second multiplexer 3 and the internal highway 12 are fed to address

0 is the input of the memory block 4, to the information input of which information is entered into the register 8. The synchronization block 1 and the first control block 5 form the necessary timing diagram for recording information in block 4, during which the color characteristics are entered into the corresponding cell of the block 4. At the same time, to build a fragment of an image of the same color, it is sufficient to enter the codes of the color components into the register 8 once, and then only output the addresses of the point records.

In the mode of erasing the screen to the first control input of block 9, the signal of the initial setting of the LL is given, at which block 9 resets the register 8 to zero and generates a start pulse of the second control block 6, which produces a pulse of one frame of display switches multiplexers 2 and 3 in such a way that the outputs of counters 4 and 10 are connected to the address input of block 4. The first control block 5 generates a write cycle whereby zero information from register 8 is written into all cells of block 4, l thereby erasing an image. The selection of the screen erase cycle is performed by frame sync pulses (XIs coming from the synchronization unit 1 to the second control unit 6.

Claims (1)

Thus, the invention provides an increase in speed by providing a complete erase mode of the entire screen and reducing the amount of recorded information when recording fragments of an image of the same color. Invention Formula A device for displaying information on the screen of a cathode ray tube (CRT), comprising a synchronization unit, first and second multiplexers, a main memory unit, the first and second control units, a video signal conditioner, a register and a interface unit, the first output of which is connected to control input of the register, the first output of which is connected to the information input of the RAM block, whose address input is connected to the output of the first multiplexer through the internal highway, the first control input of which oh, the first control input of the second multiplexer and the synchronous input of the second control unit are connected to the first output of the unit synchronization, the second output of which is connected to the clock input of the second control unit, address, first and Q Q 5 Q 5 0 five The second control inputs of the sample are connected respectively to the second, third and fourth outputs of the interface block, the fifth output of which is the output of the word code — the state of the device whose information input is the information input of the interface block whose address input is address - the device's device, the initial installation input of which is the input of the initial installation of the interface unit, the control input of which is the input signal of the device call signal, the address input of the interface conjunction block The first output of the second control unit, the second output of which is connected to the first control input of the second multiplexer, the output of the operating memory unit is connected to the information input of the video signal generator, the first and second synchronization inputs of which are connected to the third and fourth outputs of the synchronization unit, the output of which is connected to the control input of the video signal conditioner and the first address input of the first control unit, the sixth and seventh outputs of the synchronization unit are connected to info the input inputs of the first multiplexer, the output of the video signal generator is the output of the device for connection to the CRT modulator, characterized in that, in order to increase the speed of the device, it contains the first and second address counters, the outputs of which are connected to the information inputs of the second multiplexer which is connected via an internal highway to the address input of the RAM unit, the first control input of which is connected to the eighth output of the synchronization unit, the first output of which is under The key is connected to the second control input of the RAM and to the first control input of the second multiplexer, the second control inputs of the first and second multiplexers are connected to the second output of the register, the clock input of which is connected to the second output of the interface block, the gate input of the register is connected to the third the output of the second control unit, a quarter output of which is connected to the second address 514782466 the first input of the control unit, the main memory, the sixth output, the third address input of which, and the gateway are connected to the information, the control input of the first multiplexer and control inputs of the first plexer are connected to the fifth output and second address counters, secondly the control unit; the output; the variable inputs of the register and the second control unit connected to the control unit are informat the third control input the blocking input of the device.