SU1522272A1 - Device for displaying information on tv indicator screen - Google Patents

Abstract

The invention relates to automation and computing and can be used to display information from a computer. The purpose of the invention is to increase the speed of the device. The device contains a buffer memory block 1, the first 2, second 3, third 4 and fourth 5 blocks of RAM, the first 6, second 7 and third 8 control blocks, the first 9 and second 10 multiplexers, write address addresses 11 and read 12, the register 13, the first 14 and the second 15 shift registers, the character generator 16, the fixed memory block 17 and the raster word generator 18, the address generator 19, the OR element 20, the television indicator 21 with corresponding links. An arbitrary array of commands and character codes of one frame is stored in block 1 of the buffer memory. In memory block 5, the addresses of the first words of each command and the ordered coordinates of the character strings are stored. In memory block 2, codes for the backlight lines for one television line are stored. Blocks 6, 7, 8 of control, analyzing information from blocks 1, 2, 5 of memory, issue 16 character codes to arbitrary generator, located in arbitrary places on the screen, and only non-empty zones of blocks 1, 2, 5 of memory are read, this results in an increase in the speed of the device. 1 hp ff, 8 ill.

Description

Strova words, shaper 19 addresses, element 1 SHI 20 ,, television indicator 21 with the corresponding ST -, W. A random array of commands and character codes of one frame is stored in block 1 of the buffer memory. In block 5 of the memory, the addresses of the first words of each command and the ordered coordinates of the character strings are stored, in block 2 of the memory, the codes of the backlight lines are stored

for one TV line. The control units 6, 7.8, analyzing the information from the memory blocks 1,2,5, issue 16 character codes to the character generator, located in arbitrary places on the screen, and. Only non-empty zones of the memory blocks 1,2,5 are accumulated, due to which an increase in the speed of the device is achieved. 1 hp f-ly, 8 ill.

20

The invention relates to automation and computing and may

be used to display information from a computer.

The purpose of the invention is to improve the speed of the device.

FIG. 1 shows a block diagram of the device j in FIG. 2 - structure of the third control unit; on js of fig. 3 - the first control unit; 4, the second control unit; in fig. 5 form the word raster word; in fig. b - block diagram of the operation of the first control unit; on „.fig. 7 is a block diagram of the operation of the third control unit; Fig.8 is a block diagram of the algorithm of the raster word shaper

The device contains the date block 1 buffer-. memory, the first 2, the second 3, the third 4. and the fourth 5 blocks of RAM, the first 6, the second 7 and the third 8 control blocks, the first 9 and

second 10 multiplexers, counters of d "write addresses 11 and read 12, first register 13, first 14 and second 15 shift registers, character generator I6s consisting of a fixed memory block 17 and raster 18 raster 18, words 5 shaper 19 addresses, the element OR 20 and the indicator 21. The positions 22-57 in FIG. Figure 1 shows the links between device blocks.

The third control unit 8 contains V.TOR.OOY 58, third 59, fourth 60, fifth 61 registers, first 62, second 63 and third 64 reversible counters, first 65, second 66, third 67 and fourth 68 comparison blocks, the third is 69, the fourth is 70, five and 71 multiplexers, five, sixth, 73, seventh 74 and eighth 75 units are comparable, the first

55

0

s „

„, -

five

76, second 77, third 78 and fourth 79 triggers, VO's first encoder. : The first control unit 6 contains the first 81, the second 82, the third 83 and the fourth 84 counters, the sixth register 85, the sixth multiplexer 86, the fifth 87, and the sixth 88 triggers, the ninth 89s the tenth 90, the eleventh 91 comparison blocks, the second encoder 92, the second control unit 7 contains a generator of 93 clock ig pulses, a frequency divider 94, fifth 95 and sixth 96 counters, seventh 97 and eighth 98 triggers, third encoder 99.

The raster word former 18 contains the seventh 100, eighth 101 registers, the seventh 102, eighth 103 counters, the distributor 104 shshuls, ninth 105, tenth 106, eleventh 107 and twelve 108 triggers, twelfth .109 and thirteenth 110 comparison blocks, seventh multiplexer 111, the first 112, the second 113, the third 114, the fourth 115, the fifth 116, the sixth 117 AND-NOT elements, the second 118 and the third 119 elements 1 SHI.

The device works as follows.

Block 1 contains information from a single video frame of an image received from a source of information on information inputs 45. The information in block 1 is encoded by display commands. Each command contains data on the beginning of the formation of characters along the X axis (X) and information on character codes. The commands in block 1 are written arbitrarily, without ordering. Each display command occupies a certain number of words (e.g., K-2) in block 1 and is stored there at consecutive addresses. Each word source is followed by

a synchronization signal that is input to the device 45

In the fourth memory block 5, the addresses of the first words r of each command are stored in block 1 of the buffer memory and the lower bits of the data about the beginning of the formation of signs along the Y axis (YH). The most significant bits of the U (c) are the senior bits of the address of the block 5 of the operative memory and determine the partition of the address space of this memory into zones. In each zone 5, the data words are arranged in order of the lower order bits. Y .. At the same time,) 5 if there is a group of data related to the same Y value, then block word 5 storing the least significant bits YH is common to such

52 forms a signal of readiness for data output, which enters the block. At the same time, data words related to the (Yt-c) -th line are read from block 2 and their bits are distributed as follows: bits that determine the starting addresses of commands in block 1 set the counter 12 from the input 27 at the command at input 50 from block 6, and the bits of the backlight line codes are written to register 13 at the command at input 50 from block 6. Then, at the command at input 44 or block 7, the word of block 1 is read at the address set in counter 12, which arrives at the address inputs of block 1 through multiplexer 10. Control of multiplexer 10 is carried out Group, it has a special bit, 20 signal on the input 44 from block 7.

The first word of the display command, which defines X, is read from block 1 and enters 46 at the inputs: the most significant bits are in the address generator 19

placed first in the group and referred to as indicative. In the absence of data related to any value of Y, there is no corresponding sign word. So about-25 (xhozmand - at exit 42 from block 7

all at once, the data in any zone of block 5 is stored so that empty addresses in their sequence are excluded. Therefore, the sign of the end of data in any zone is the first empty word, which contains zeros in all bits. Such storage of data in memory block 5 avoids wasting time on reading empty addresses.

In block 2, the RAM is stored. The initial addresses of block 1 are combined with the current values of the codes of the backlight lines related to one TV line .. The array stored in block 2 is also organized in such a way that it does not contain empty addresses in the intervals between the stored data, the first empty word is therefore a sign of the end of the data.

The formation of images of groups of characters arbitrarily placed on the screen of the television indicator 21 is carried out as follows.

thirty

35

control), the least significant bits are in the raster word generator 18 (the command is at output 30 from control block 7). Then, the signals at input 50 from block 6 realize single increments of counter 12 and the character codes read from block 1 by inputs 46 alternately arrive at block 17 of the character generator 16. At the same time, the bits of the address of block 17 corresponding to the codes of the backlight lines are read from register 13 through signals at output 28 from block 7.

At the same time, the word of block 2 via outputs 27 enters block 6. In this block, the value of the code of the lines of the backlight is increased by 1 and it is analyzed whether it has become equal to the number of expansion lines by the plus sign 1. If this condition is not met, the word of block 7 through inputs 24 through multiplexer 9 returns to block 2 with a new value 40

code lines highlighting. Otherwise

In the process of forming the TV 50 case, the word is not returned to block 2, the on-screen raster from control block 7 to, since the display of this group of characters by control block 8 through communication 51 arrives at the current frame is completed, the code corresponding to the value Y. Unit increments of the counter 12 and the upper bits of this code are the reading of the character codes of the same command block 5 addresses, the lower ones using the display from -55 of block 1 continue to search for that data in block 5,. to the value of the last address of this

which relate to (row. After such data is found, block 8 at one of the outputs

commands determined by block 6. Thereafter, the counter 12 enters the input 12 from block 2 and receives the start address; the next one, 52, generates a readiness signal for data output, which goes to the block. At the same time, data words related to the (Yt-c) -th line are read from block 2 and their bits are distributed as follows: bits that determine the starting addresses of commands in block 1 set the counter 12 from the input 27 at the command at input 50 from block 6, and the bits of the backlight line codes are written to register 13 at the command at input 50 from block 6. Then, at the command at input 44 or block 7, the word of block 1 is read at the address set in counter 12, which arrives at the address inputs of block 1 through multiplexer 10. Control of multiplexer 10 is carried out Signal by the input 44 from block 7.

0

five

control), the least significant bits are in the raster word generator 18 (the command is at output 30 from control block 7). Then, the signals at input 50 from block 6 realize single increments of counter 12 and the character codes read from block 1 by inputs 46 alternately arrive at block 17 of the character generator 16. At the same time, the bits of the address of block 17 corresponding to the codes of the backlight lines are read from register 13 through signals at output 28 from block 7.

At the same time, the word of block 2 via outputs 27 enters block 6. In this block, the value of the code of the lines of the backlight is increased by 1 and it is analyzed whether it has become equal to the number of expansion lines by the plus sign 1. If this condition is not met, the word of block 7 through inputs 24 through multiplexer 9 returns to block 2 with a new value 40

In this case, the word in block 2 is not returned, since the display of this group of characters in the current frame is completed, the unit increments of the counter 12 and the reading of the character codes of one display command from block 1 continue until the value of the last address of this

commands determined by block 6. After that, the counter 12 enters input 27 from block 2 and receives the start address of the next 71522272

command and converts the character codes to video codes before completing the processing of all the commands of block 1 related to the television line,

YT-H

By this time, the data of those commands related to the () -th TV line will remain in block 2. If in block 5 there is data related to this line, then they are from block 5 are rewritten to block 2 via multiplexer 9 by the signals at inputs 56, 22, 23, 52, 53 from blocks 8 and 6. Thus, by the end ( t + () of the 15th row in block 2. there will be all the data related to (row.

This process is repeated on each television line until the completion of the 20 imaging of the entire frame.

The formation of video codes of signs is closed in that each raster line is divided into groups of raster elements, called raster 25 words. The television image of a single line is formed by an ordered sequence of raster words. For this, the X coordinate code splits8

Lou at exit 30 from the block with in one of the blocks 3 or

Raster words count 3 or 4 and the inputs 3 step into the registers 14 of the mud, which form the video parallel video. The outputs are connected to the inputs ale the output signal from which to the video input of the television 21. The signals of the synchronization of the raster are received on the input 41.

Registers 14 and 15 are operative when a set of write / read signals 37 from block 7 is affected. If, if register 14 is written to B10 in a parallel code, time from register 15 in the serial code. These functions are reversed.

Inputting HOBbix data is performed by following the common address of the command into a block from the source of information.

from to two components, the first of which sets a 1t counter

It also carries information about the number of the raster word counted from the beginning of the television line (most significant bits). The second component X corresponds to the number of the element counted within 35 raster words (lower bits Hz). Older X.Js at Exit 46 come in.

H

the address generator 19 for addressing that block 3 of the 4, which is currently 40 in writing.

Raster words are formed as follows. When the signal at output 30 from block 7 is applied, the raster word generator 18 enters the video codes of the string of this symbol at inputs 31. Shaper 18 provides the Shift of this code by the number of elements, determined by the lower bits of the Hc code, as well as the storage of this video code until the end of processing, the symbolic command. For the next character, the process is repeated with the difference that the amount of video code shift increases by the number of elements in the line of one character plus the space between the characters. After the procedures for forming a raster word are completed, it is signaled to one of the buses 44. The second word to the Liver comes in and is stored in one of the buses 44 from the block. All subsequent (K-2) slits are entered in block 1 of the buffer signals at input 44 from lazy 1 1 1 implemented by the block. 7 at the entrance 44.

The search for the address of block 5 must be recorded explicitly in block 1 and the least significant is released simultaneously with the data from this block. In the search, in block 8, the memorization of the address of the first empty ka 5 in the zone in which the new data is entered is the number of words in block 5, the count of the address at which the new data is entered, before the zone.

The procedures for recording the new data block 5 to the personnel personnel extinguishing it with the result of

eight

At output 30 from block 3, it records into one of blocks 3 or 4 of memory.

The raster words are read out from block 3 or 4 and, through inputs 35 and 36, go to shift registers 14 or 15, which form the video signal, converting the parallel video code to serial. The outputs of registers 14 and 15 are connected to the inputs of the element OR 20, the output signal from which is fed to the video input of the television indicator 21. The raster sweep synchronization signals come from the control unit 7 on the input 41.

Registers 14 and 15 work alternately under the influence of write / read control signals on inputs 37 from block 7. If, for example, a raster layer B10 is written to register 14 in a parallel code, at the same time, data in serial 15 is output from register 15 . Upon completion, the register functions are swapped.

HOBbix data is entered into the device in the following way. The starting address of the command in block 1 comes from the source of information and from input 45

sets counter 1t

for permission on one of the tires 44 from the control unit 7. The second command word, containing Yc, is received by the p control block 8 and is stored there by a signal on one of the buses 44 from the control block 7. All subsequent (K-2) command words are entered into the block 1 of the buffer memory by the signals at input 44 from the block 7 control for unit increments of the counter 1 1 carried out from the signals of block 7 at input 44.

The search for the address of block 5, on which the newly entered into block 1 and the least significant bits Y) should be recorded, is carried out simultaneously with the reading of data from this block. As a result of the search, in block 8, the value of the address of the first empty word of block 5 in the zone in which new data must be entered, as well as the number of words of block 5, counted from the address at which new data must be entered, is memorized, until the end of the selected zone.

The recording procedures of the newly inputted into data block 5 are carried out during a frame damping pulse. As a result of these procedures

new data is entered into a given zone of block 5 with reference to the scan line that corresponds to the lower-order bits of Y, without gaps between the data within each of the zones and maintaining the order, both in this zone and in the block data array five.

In the erase mode, the lower-order bits of the current dwell addresses of block 1 from the information source are written to the corresponding information Q, zeros. The address search is deleted in block 2 at the same time as reading

this data. As a result of the search, block 8 stores the address. Deleted data of block 5 and the number of words of the third block counted from the deleted address to the last address in zone a. Deletion of data from block 5 occurs during a frame damping pulse. As a result of the implementation of these procedures, the data in the zone of block 5 remains unchanged and ordered.

The device does not require the ordering of the displayed data, received from the source, and allows you to make changes to the displayed data without affecting the entire array of displayed data, 4, b, 7, a sequence is formed

control signals, which ensure that data from block 2 of memory is copied to sequential addresses prior to the arrival of any feature word

35 (a signal is generated at the output of block 73 and input 9 of the encoder 80), or a zero word (a signal is generated at the output of block 72 and input 11 of the encoder 80). In the first case, the signal is removed.

40 readiness on one of the output tires 52 of the block (code 5 of the encoder 80), the formation of single increments of the counter 62 is stopped based on the signals from exit 7 of the counter 80 and is reset

45 trigger 76 on the signal from the output 27 of the encoder 80. Thus, in this case, after completing the reading and transmission of all data, the block 2 of the memory related to (O-line O, in

50 counter 62 will be set to address

feature word block 2 of the memory related to one of the next TV lines of the same zone.

and change only that part that relates to the data being changed. , .

The control unit B is designed to form an ordered array of initial command addresses of the displayed data in the first block of memory 2, match it with reference to the current television scan line number and output to the second memory block 3 through the first multiplexer 10, a. also the generation of t1 alignment signals for memory block 2 and readiness for control block 6.

The block diagram of the block operation in reading, writing and erasing modes is presented in FIG. 6 (a, b, c).

In the initial state, all the registers, counters, and triggers of the control unit 8 are in the reset state. In the read mode, the horizontal frequency pulse (sen) arriving at the input of the block, one input 51 to the input 3 of the encoder 80, at its output 4 and the output bus 56 generates a reading signal for memory block 2. At the same time, the address of memory block 2 is determined by the output code of counter 62 (lower address bits), arriving at output 55 through 55

In the second case, the presence of the zero word means the end of the data reading, referring to w1-xc to one zone of the memory block 2. Therefore, at output 10 of the encoder 80, a reset signal is generated.

cut multiplexer 70, and code. (senior address addresses) j arriving at the bus 55 through the multiplexer 71 with the input bus 51.

The data word of block 2. The memory from the input bus 57 is fed to the input of the compare block 68 (smaller bit Yj), to the other inputs of which from the tires 51 of the TV line increased by 2 (YT + U) and the comparison resolution signal from output 25 encoder 80, which is formed by the indicative

the word read from block 2 is allocated to the word allocated by block 73, the signal from which is fed to the input 9 of the encoder 80. When the lower bits of YH and YT- / T are output, the trigger 76 is set from block 68, the output signals of which are fed to the inputs 11, 12 of the encoder 80. The encoder 80 at the output 5 and on one of the bus 52 generates a readiness signal vadachi

data related to (tv line).

After the arrival of the ready signal of the control unit 6 to the input bus 53 and the input 10 of the encoder 80 at its outputs

In the second case, the presence of the zero word means the end of the data reading, referring to w1-xc to one zone of the memory block 2. Therefore, at output 10 of the encoder 80, a reset signal is generated.

ch152227

 62, a cohort in each zone starts the counting of block 2 addresses from zero. : The trigger 76 is reset as well as the first century. Previous case ..

: After all the I data from block 2 is completed in one frame, they I are repeated in subsequent frames of information display.

 The appearance of the recording resolution signal JQ si (RE) at one of the input buses 44 means that the displayed data will be changed. This signal sets the trigger 78, the output signals of which are sent to the BXO-J to enter a sign word, contents 15, 16 of the encoder 80. According to the input permit signals, which are input to the input 14 of the encoder 80 on one of the input buses 44, from the input buses 45 registers 58 ,, 60 and 61 enter the initial information for the newly entered ones at outputs 21, 23 and 24 of the encoder 80. At the same time, register 58 stores the I value of the initial address of the buffered memory block 1, in register 60 - the high-order bits YH (the number of the sign of block 2), and in the register 61 - the low-order bits U ;. A signal from one of the buses 45 in the recording mode sets a trigger 77, the output signals of which are fed to the inputs 13, 17 of the encoder 80.

character trait and minor bits Yr.

In the case of a signal from the output of the comparison block 67, a trigger 79 is set at the output 15 of the encoder 80 and the increments of counters 62, 64 from the outputs 7, 18 of the encoder 80 are resolved. These increments are made until the zero word 25 is read from the output of block 72 at the input 1 of the encoder 80. This signal at the output 13 of the encoder 80 generates a signal for setting the counter 63 with data from the output of the counter 62. Thus

30 in the counter 63, the address of the first empty word of block 2 in this zone will be set, and in counter 64, the number of words of block 2, counted from the first empty address of the zone to the ad-procedure for entering new data in block 2, provide for the search for the address of this block, by which This data must be entered, and a record of this {data. The data is recorded during a frame extinguishing pulse, and the search is carried out without interrupting the data reading procedure from block 2 described above. The search procedures for block 2 addresses are implemented in the following sequence.

After the OIG arrives, the new data is entered into block 2, taking into account the ordering of their order as follows: First, all the data in block 2, starting from that address where the new information is entered, is shifted to the right by the end of the third address ( address increment)

Block 66 compares the high order bits Yz, stored in register 60, from 45.

high-order bits Y – r + 2. I arrive at the signal from the output of the 9 M encoder from one of the input buses 51. When comparing these values, which correspond to the fixing of the beginning of the zone of block 2,

80, the counter 82 is set by the output data of the counter 63. Then, the signal at the output 8 of the encoder 80 and the contents of the counter 62 rolls over 1, which ensures that the last address in this counter is set to the zone over which the data is recorded. According to the signals at the outputs of 4, 2 cipher

To which new Data should be entered, the comparison block 66 forms a signal which is fed to the input 6 of the counter 80. The output of the encoder 80 is allowed to work

50

80, the counter 82 is set by the output data of the counter 63. Then, the signal at the output 8 of the encoder 80 enters 1 from the contents of the counter 62, which ensures that the last address of this zone in which the data is recorded is set in this counter. According to the signals at the outputs of 4, 2 cipher | 5 blocks 67, which compares the younger 80 to the word read from the block

bits Уц and Ут, 2. ° time, presence of 2, is recorded in register 59, and then the code signal at the output of block 73, and signals at the outputs O, 1, 4 of the encoder 9, encoder 80, i.e. at the time (a sign of the word.

on the signals at the outputs of O, 1.4

the torus 80 through the multiplexer 69 records back, but at the address.

If the compare block 67 generates a signal (arrives at the input 4 of the encoder 80), then this means that from block 2 there is already data relating to the same line as the entered ones, if a signal is generated by the comparator (fed at input 5

ishfratora 80), this means that there is no such data. Therefore, in the first case, one word should be entered in block 3 (the starting address of memory block 1), and in the second case two words: in addition to the starting address,

character trait and minor bits Yr.

In the case of a signal from the output of the comparison unit 67, a trigger 79 is set at the output 15 of the encoder 80 and the increments of counters 62, 64 from the outputs 7, 18 of the encoder 80 are resolved. These increments are made before reading the zero word from the output of block 72 at input 1 of the encoder 80 This signal at the output 13 of the encoder 80 generates a signal for setting the counter 63 with data from the output of the counter 62. Thus

counter 63 will set the address of the first empty word of block 2 in this zone, and counter 64 will set the number of words of block 2, counted from the first empty zone address to the address of memory block 2, over which new data should be entered.

After the OIG arrives, new data is entered into block 2, taking into account the order of their ordering, as follows. First, all the data in block 2, starting from the address where new information is entered, until the end of the zone is shifted by one address to the right (in the direction of increasing addresses) as follows

.

The signal from the output 9 encoder

0

80, the counter 82 is set by the output data of the counter 63. Then, the signal at the output 8 of the encoder 80 enters 1 from the contents of the counter 62, which ensures that the last address of this zone in which the data is recorded is set in this counter. The signals at the outputs 4, 2 of cipher 2 are written to register 59, and then the signals at the outputs O, 1, 4 are ciphered by the signals at the outputs O, 1.4

the torus 80 through the multiplexer 69 records back, but at the address.

installed in the counter 62. Then the signals at the outputs 8, 12, 17 of the encoder 80 from the counters 62, 63 and 64

subtracted 1 These procedures go on, at the end of the zone, by empty addresses, then they go through until a zero code is set in counter 64, fixed by block 75, the output signal from which enters input 19 of the recording cipher procedures are implemented immediately. They are similar to those described above, the difference is only in the initial entry into the counter 64 of the code 0 ... 01 and the increase

rrator 80. This is the case with content 1 of counter 63, and

There is a setting in the counter 62 of the address of block 2, on which new data must be entered.

Therefore, according to the signals at the outputs O, 1, 4. of the decoder 80, the data from the register (58 through 69 are recorded in block 2 "After the completion of these procedures, the outputs 10, 14, 16, 19, 20, 27 of the encoder

In erase mode, trigger 77 is not set. In this mode, the starting address of memory block 1 is removed from register 2 in register 58, and in registers 60 and 61, the high and low bits of Y are set; respectively. Older units U ,. compared to 80, the reset signals of all the registers, counters, and triggers are generated. In this 20 value by block 66, and in case if block 67 generates a case of equality of the output signal, in block 2 there should be a comparator on input 6 of the decipher- 2 words are written. In this case, trigger 79 is not set, but the number

Rattor 80, On this signal, the encoder 80 at the output 26 forms the resolution

2 words read from the block 2 are considered 25 comparisons of the lower bits Yz and Y .. a counter 64 before the arrival of the first block 67. In this mode,

zero word in this zone. Then

ra, on which the transmitter 80 signal at the output. 22 allows comparing block 30 of data from register output 58 with data read from block 2 of memory.

The signal from the output of the block 65 is fed to the input 2 of the encoder 80, which increases the contents of the counter 63 - 35 allows the counter 63 to be set to i by the output signal 11 of the output of the counter 62, as well as the installation of the trigger 79 from the output 15 of the encoder 80 and account +1 counter 64.

The trigger 70 fixes the case where the 4Q word, block 2 is the only one on this line, which corresponds to the removal of two Sshovs in this zone and requires shifting the words to two addresses in the direction of decreasing them. In this case, the installation of the trigger 79 is performed anyway, but if the deleted data does not immediately follow the indicative word and is not immediately followed by the indicative word, the output through the multiplexer 69. Then the block 50 16 of the encoder 80 forms signal 75 will be fixed code 0 ... 000 with reset of this trigger, the output of counter 64. According to the signal from the output, data erasure procedures of the analyzer 75 of the encoder 80 in this case generate signals at the outputs O, 1, 4 of the encoder 80, provide -.55 is installed, then the counter 62 is a decisive entry in block 2 data from the register: pours over the counter 62, into the counter 62 61 through the multiplexer 69 with the input of the sign bit, i.e. record indicative. After that, the forcing counter 63 is set by patch 62 and the recording procedures are terminated until the OIG arrives.

With the arrival of the OIG, the count 62 is set at the counter 63. Then the content of the counter 62 is reduced by 1 according to the signal at the output 8 of the encoder 80,

Rattor 80, which achieves the installation of the last written word in the zone of addresses of RAM with a shift of 2 in a big way.

. Procedures for overwriting block data. 2 with a shift similar to those described above, they continue until the block 74 detects the code 00 ... 01 from the output of the counter 64. The signal at the input 18 of the encoder 80 from the output of this analyzer at the outputs O, 1, 4 of the encoder 80 generates signals that provide the words block 2 with register 58

during the OIG and are determined by the state of the trigger 79. If the trigger 79

unit is added, then the data from block 2 is read out by lr res, determined by counter 62. their

Miraugs reset signals all counters, triggers and registers. In this case, if new data is entered into

records are implemented immediately. They are similar to those described above, the difference is only in the initial entry into the counter 64 of the code 0 ... 01 and the increase

so that in this case the first word is entered.

In erase mode, trigger 77 is not set. In this mode, in register 58, the initial address of memory block 1 is set to be removed from block 2, and in registers 60 and 61, the high and low bits of Y are set; respectively. Older units U ,. compared to the current 1m value by the block 66, and if they are equal, the comparator signal is sent to the input 6 of the decoder 6

 the value of the block 66 and in the case of equality, the output signal of the comparator is fed to the input 6 decipher

Rattor 80, On this signal, the encoder 80 at the output 26 forms the resolution

Only the signal from this Comparato Trigger 70 fix1 is the case where the word, block 2 is the only one on this line, which corresponds to the removal of two Sshovs in this zone and requires shifting the words to two addresses in the direction of decreasing them. At the same time, the installation of the trigger 79 is performed anyway, but if the deleted data does not immediately follow the indicative word and is not immediately followed by the indicative word, the output of the 16 encoder 80 produces a reset signal for this trigger. - installed, then the counter 62 is installed; it is poured over the counter 62, into the counter 62

during the OIG and are determined by the state of the trigger 79. If the trigger 79

The trigger 70 fixes the case where the word, block 2 is the only one on this line, which corresponds to the removal of two Sshovs in this zone and requires shifting the words to two addresses in the direction of decreasing them. At the same time, the installation of the trigger 79 is performed anyway, but if the deleted data does not immediately follow the indicative word and is not immediately followed by the indicative word, the output of the 16 encoder 80 produces a reset signal for this trigger. - installed, then the counter 62 is installed; it is poured over the counter 62, into the counter 62

unit is added, then the data from block 2 is read out by lr res, determined by counter 62. their

writing to regisgr 59, and then writing to block 2 at addresses determined by counter 63. After that, the contents of counters 62 and 63 are incremented by 1, and the contents of counter 64 are reduced by 1. These procedures continue to install counter 64 and, respectively, the signal. At the output of block 75. At the address of block 2, the corresponding moment of the signal from block 75, zeros are recorded through multiplexer 69, and then the reset signals of all the registers, counters, and triggers are generated.

If trigger 79 is set. The shift of data to 2 addresses in the direction of decreasing them is performed as follows. Counter 62 is set to counter 63, and then the contents of counter 62 are incremented by 1, and the contents of counter 63 are decreased by T. The address of block 2 is read at the address specified in counter 62, written to register 59, and then returned to block 2 but at the address determined by the counter 63. After that, the contents of the counters 62 and 63 increase by 1, and the contents of the counter 64 decrease by 1 until blocks 74 and 75 lock the codes on. the output of counter 64 is first 10 ... 01, and then 0 ... 000. At the addresses | of block 2, by the time corresponding to these | codes, zeros are written. The erasure procedures are also erased, and in this case, the end of the process is reset by all registers, counters, and triggers. I Thus, when deleting data

| from the array stored in the 2 p m block - Q of which is fed to the input 4 of the encoder 92. If the code at the output of counter 83 corresponds to the number of character decomposition lines (CHSRZ) plus 1, then at the output of the block 89, the encoder 92 at output 2 forms the increment signal of the counter 82. If the code at the output of the counter 83 does not correspond to this level, then the signals are written to the data word in the memory block 3 at the output 4 of the encoder 92. The address of the memory block 3 through communication 2.6 is set to output-to one counter 81, and the input data 24 - the contents of the register 85 and the counter 83. After completing the recording procedures, the counters 81, 82 are incremented by the signals at the outputs 1, 2 of the switch 92. At the same time, the encoder 92 at the top of all. 9 generates signals from the circuit, its orderliness, as a whole, and continuity in each zone is preserved.

Comparison blocks 72-75 are AND-NOT circuits with direct inputs of signals 1 and inverse - for 45 O. They form level 1 at the output when a given code arrives at their inputs.

 The control unit 6 is designed to form the address and control signals — Lenin of the 3 memory block, storing, processing and analyzing one word of this il-o block, generating signals of different times 1) after installing the counter 12 and recording signal in register 13; the control signals of the multiplexer 10 and the ready signal applied to the control block B.

The block diagram of the block operation algorithm is presented in FIG. 7, In the initial state, all the counters, register, and triggers are in the reset state. The operation of the block on each television line begins with the installation of the trigger 87 with the leading edge of the horizontal damping pulse (SGI) entering the block input via one of the busbars 43. The encoder 92 forms a sequence of control signals that provide the following actions,

The signal at output 4 of the encoder 92 reads the data word of block 3 at the address determined by the counter 82, the outputs of which are connected to the address inputs of memory block 3 by communication

26 through multiplexer 86 .. Read word from communication block 3

27 enters block 91 and, if it does not contain zeros in all bits, is memorized as follows: bits that determine the address of memory block 1 in register 85, and bits that determine the codes for the backlight characters (XI) in counter 83. At the same time, the output 6 of the encoder 92 generates a signal to write to the register 13 and set the counter 12. Then, the output signal 10 of the encoder 92 in the counter 84 sets a code corresponding to the number K-2, where K. is the number of words in one command display, and the contents of the counter 83 is added 1. The code at the output of the counter 83 is analyzed by block 89, the output signal

which is fed to the input 4 ciprato

92. If the code at the output of counter 83 corresponds to the number of character decomposition lines (CHSRZ) plus 1, then the signal at the output of block 89 encoder 92 at output 2 generates a single increment signal of counter 82. If the code at the output of counter 83 does not correspond to this level then the signals are written to the data word in the memory block 3 at the output 4 of the encoder 92. At the same time, the address of the memory block 3 via communication 2.6 is set to output one to counter 81, and the data at input 24 is recorded by the register 85 and counter 83 The unit completes the recording procedures by a single increment. counters 81, 82 by the signals on the outputs 1, 2 schnfratora 92. Simultaneously, the encoder 92 on vk.ode 9 generates signals subtracting 1 from the contents of the counter 84, which is analyzed by unit 90.

A signal from the output of block 90, which is fed to the input 7 of the encoder 92, at which input 4 of which a read signal of the subsequent word of the memory block 3 is generated. These procedures continue until the zero word of the memory block 3, which is fixed by the block 91, is read.

The output signal of the block 91 is fed to the input 9 of the encoder 2. If the signal

20

On one of the inputs 52 of the read / write absence of registers 14 and 15. On output 11 of the encoder 92, a reset signal is generated for all counters, flip-flops and a register.

If there is a ready signal on one of the buses 52 of the python 92 at its output 12, it generates a trigger setup signal 88, the output of which is fed to the input 8 of the encoder 92, which in this case, at the outputs 4, 1, generates the switching signals of the multi-25 plexer 86, recordings in block 3 of memory and single increments, of counter 81 by signals +1, entering the block input through one of the inputs 52, before sn - .. ready signal tone. After that, jO at the output 11 of the encoder 92, a reset signal is generated for all the counters, flip-flops and a register. All the above procedures are repeated with the arrival of each GIS signal.

Epoque 7 is designed to form synchronous 1x and control signals that provide synchronous and in the required sequence the operation of all blocks of the device.

The pulse generator 93 generates two pulse sequences that are phase-shifted relative to each other. One of the sequences of synchronizing pulses goes to frequency divider 94. The output signals from the pulse generator 93 and from the frequency divider 94 arrive at inputs 1-6 of the encoder 99. At outputs 1-3

From the outputs 5, 7, 8 and 9 of the encoder 99 to the output 30, the clock signals + 1, the signals for recording the lower-case video codes of the characters and the signals for the lower bits of Hz are received, respectively.

From outputs 9 and 10 of the encoder 99 to output 42, signals are written to write the high bits X j and the increment of addresses of the address former 19.

Data word tracking signals (BTS) over communication 45 are fed to the input 7 of the encoder 99. The number of received BTS signals is equal to the K-number of words in the command. With the help of the signals of the SSB, which are fed to the input 7 of the prffrarator 99, the signals from the output of the counter 45, the signals to the input 8 of the encoder 99, and the flip-flops 97 and 98 of the cipher, the torus 99 forms the following signals on the output buses of the block.

The first two words of the SSP form the signals at the output 19 of the recording resolution encoder 99, which arrive at the output of the block via communication 44. The first SPS at the output 12 of the encoder 99 generates the installation resolution signal of the Counter 11, which enters the code of the block one by one from links 43 and 44, to the other link 43, D5 SGI is received from output 13 of the encoder 99.

Subsequent signals of the ERPs at the course of 15 of the encoder 99 form the increment signals of the counter 11, which in one of the links 44 are sent to

35

40

encoder 99, synp output block signals are generated. On the same tires come

Chronizavdsh television indicator 21 in rows and frames, as well as lowercase and. personnel damping pulses, which, via communication 41, arrive at the output of the block. Frame and line sync pulses also arrive at counter 96, on whose output buses signals are generated Counter 96 at the beginning of each frame is set to 55

the read / write control signals of the memory unit 1 and the multiplexer 9 from the code 14 of the encoder 99.

SSP signals are also received at input -1 of counter 95, which is set by the number K-1 before the arrival of the SSP. Therefore, after the arrival of the last signal of the SSP, counter 95 forms a loan signal, which is fed to input 8

+2 frame synchronization by a pulse, and then individual increments are made on every 11 television lines. Signals Y., together with horizontal synchronizing pulses, frame extinguishing pulses from code 4 encoder 99 and clock signals from output 5 of encoder 99 arrive at output 51.

With the output 6 and 8 of the encoder 99, the high-frequency clock signals and the signal 0 come to the output 37 of the block

 read / write registers 14 and 15.

5 .. O

From the outputs 5, 7, 8 and 9 of the encoder 99 to the output 30, the clock signals + 1, the signals for recording the lower-case video codes of the characters and the signals for the lower bits of Hz are received, respectively.

From outputs 9 and 10 of the encoder 99 to output 42, signals are written to write the high bits X j and the increment of addresses of the address former 19.

Data word tracking signals (BTS) over communication 45 are fed to the input 7 of the encoder 99. The number of received BTS signals is equal to the K-number of words in the command. Using signals SSP, the input to the input 7 of pshfratora 99, the signals from the output of the counter 45, the input to the input 8 of the encoder 99, and the trigger 97 and 98 encoder 99 generates the following signals on the output buses of the block.

The first two words of the first two words are formed at the output 19 of the encoder 99, recording resolutions, which arrive at the output of the block via communication 44. At the first output of the encoder 99 at the output 12 of the encoder 99, the installation signal of the Counter 11 is generated, which enters the code of the unit through one of the Zey 43 and 44, the D5 SGI from the output 13 of the encoder 99 enters the other link 43.

Subsequent signals of the ERPs at the output 15 of the encoder 99 generate the signals of the primer of the counter 11, which through one of the links 44 arrive at

five

40

five

the read / write control signals of the memory unit 1 and the multiplexer 9 from the code 14 of the encoder 99.

Signals of the ERPs are also received at input -1 of counter 95, which is set by the number K-1 before the arrival of the ERPs. Therefore, after the arrival of the last SSP signal, the counter 95 generates a loan signal, which is fed to the input 8

encoder 99. The signal for resetting: during course 17 of encoder 99 produces a reset signal for flip-flops 97 and 98, and then output 16 for an installation signal; counter 95, the final reception of K words from an information source (not shown), I Shaper 18 is designed to form a raster word that corresponds to the video codes of a given i to generate a signal at the output if

groups of characters on each television line, taking into account the intervals between the characters, as well as their location on the screen, taking into account the lower bit Hz.

In the initial state, all the registers, counters, pulse distributor, and triggers are in the reset state. According to the record enable signal of the lower bits X, which comes to the input of the block via one of the links 30, these data are entered into the register 101. Then, using the Recording signals (WL) that go to one of the inputs 30, a parallel input is made dannk from input 31, taking into account the spacing between the characters. Trigger 105 is set by the signal of the RFP, and in the counter 102, through the multiplexer 111, a code corresponding to the number of elements of the displayed characters is taken into account, taking into account the intervals between them -1. The trigger 105 allows the passage of high-frequency clock pulses.

(BT) from One of the inputs 30 through the implementation of their ordering and from 4 to 112 to the register shift input: in block 5, only

100. The same clock signals come in the lower part of Y, which is determined by input -1 of counter 102. The signal is the moment of entering the initial addresses

The UM of the loan from the output of the counter 102 of the slave-block 1 of the buffer memory into the block 2,; the trigger 105 is blocked, the receipt-40 is prohibited and in the block 2 only the code values

There is a single jioe increment of the counter 103. The shift cycles of the video view codes in the i 00 register, taking into account the spaces between the digits, are repeated until the comparison MW 110 is fixed corresponding to the number of characters in the group.

A signal from the output of block 1-10 establishes a trigger 107, which blocks the passage of signals of the CC to the register 100 and the element OR 19, switches the multiplexer 111, sets the trigger 105 and the counter 02 from the register 101, and 1 allows the installation of the trigger 108 of the signal from the counter 102 and the operation

block 109 comparison. This signal will be generated after the bitmap word, xpafmMoe in register 100, is shifted by the number of pixels corresponding to the low-order bits of X. During this shift, the signals from the output of counter 102 are fed to the input of block 109, which

its input will be a code corresponding to the value of the gap between the characters, increased by 1. This signal sets the trigger 106.

The installation of the trigger 108 means that the formation of the raster word in the register 100 is completed. Therefore, the arrival of the BT signals to the shift input of the register 100 is prohibited, and the clock signals +.1 through the AND element 116 are also allowed to enter the pulse distributor 104, the output signals from which are fed to the status control inputs of the outputs of the register 100.

Thus, the invention improves the speed of the device by eliminating double rewriting of all words of each command, because only the start address of the command is copied twice in the buffer memory block 1, and at least 3 are stored in blocks 3 and 2 of the main memory. auxiliary data required

 55

The backlight lines determine the character of the video signal on each line of the television scanning of characters and the time of the starting address of the block 45 1 of the buffer memory in block 2, the data arrays in the zones of blocks 5 and 2 do not have gaps, which eliminates the loss of time for reading empty addresses.

50 Formula of invention

 1. A device for displaying information on a television indicator screen, comprising a buffer memory block, first, second and third RAM blocks, first and second control blocks, first multiplexer, register, first and second shift registers, character generator, address formater, first and the second outputs of which are connected to the first and second address inputs of the second and third blocks of RAM, whose information inputs are connected to the output of the character generator, the first address input of which is connected to the output m of the register, whose information input and the input of the feature code of the end of the U array of the first control unit are connected to the output of the first RAM, whose address and control inputs are connected to the first and second outputs of the first 15 control unit, the third and fourth outputs of which are connected respectively to the first information and control inputs of the first multiplexed input of the buffer memory block whose output is connected to the information input of the address generator and to the second and third hell The main inputs of the character generator, the information inputs of the second and third control units and the information input of the write address counter are connected to the information input of the buffer memory block, the first, second and third outputs of the third control block are connected to the information, address and control inputs of the fourth memory, the output of which is connected to the second information input of the first multiplexer, and to the input of the code of the sign of the array end of the third control unit, the fourth output of which

The copray, the output of which is connected to infor-20, is connected to the readiness signal input by the mating input of the first RAM block, the first output of the second control block is connected to the control input of the buffer memory block, the information input of which is the 5 information input of the device, the second output the second control unit is connected to the reset input of the first register, the third output of the second block of the control unit, the fifth output of which is connected to the input signal of the third control unit, the enable signal input The input data of which, the control input of the second multiplexer and the control input of the record of the write address counter are connected to the first output of the second control unit, the eighth output of which the control is connected to the control input of the third

The address generator of the address generator, the clock input of the character generator is connected to the fourth output of the second control unit whose five output is connected to the control inputs of the first and second shift registers, whose outputs are connected to the inputs of the OR element, the output of which is connected to the video indicator of the television indicator whose sync input is connected with the sixth output of the second control unit, the seventh output of which is connected to the gate input of the first control unit, the output of the second RAM block is connected to the first information Inputs of the first and second shift registers, the second information inputs of which are connected to the output of the third RAM block, different from the fact that, in order to improve the speed of the device, it contains the third control block, the fourth RAM block, the second multiplexer , address and write address counters, the outputs of which are connected respectively to the first and second information inputs of the second multi-plexor, the output of which is connected to

the address input of the buffer memory block whose output is connected to the information input of the address generator and with the second and third address inputs of the character generator, the information inputs of the second and third control blocks and the information input of the write address counter are connected to the information input of the buffer memory block, first, second and third the outputs of the third control unit are connected respectively to the information, address and control inputs of the fourth random access memory, the output of which is connected to the second information ion-input of the first multiplexer and to an input end of an array of feature code of the third control unit, which fourth output

connected to the ready signal input

the first control unit, the fifth output of which is connected to the input signal of the readiness of the third control unit, the input data enable signal input of which, the control input of the second multiplexer and the control input of the write address counter record are connected to the first output of the second control unit, the eighth century of which control, the sixth output of the first control unit is connected to the recording control input of the first register and to the recording control input of the counter

The readout health information input of which is connected to the output of the first RAM block, the clock input of the write address counter is connected to the seventh output of the second control block.

2. The device according to claim 1, of tl and - cha ate, in that the third control unit contains the second, third, fourth and fifth registers, the first, second and third reversible counters, first, second, third and fourth, p the fifth, sixth, seventh, eighth comparison blocks, the third, fourth and fifth multiplexers, the first, second, third and fourth triggers and the first encoder, the first and second outputs of which are connected to the control inputs of the third multiplexer, the first information input of which is connected to the output third register, entry. recording board which is connected to the third output of the first W: 1flotora5 fourth output to

the second is connected to the control input of the fifth multiplexer, the output of the third multiplexer is the first output of the third control block, the second with the output of which are the fourth and fifth multiplexers, the fifth output of the first encoder is connected to the control input of the fourth multiplex. Xora is the third output (the third control unit, the fourth output of which is the sixth and seventh outputs of the first encoder, the eighth, ninth, tenth and eleventh outputs of which are connected, respectively, to This is an AF1, subtracting clock inputs, output: recording control and reset input; the first reversible counter5 whose output is connected to the information input of the second-20 reversing counter and to the first information input of the fourth multiplexer, the second information input of which and the information input of the first reversible counter 25 yen with the output of the second reversible counter, summing and subtracting clock inputs, the recording control input and the reset input of which are connected to the twelfth respectively, the threeteen and fifteenth outputs of the first encoder, the sixteenth and seventeenth outputs of which are connected respectively to the installation inputs in O and in the 1st fourth trigger, pa, eighteenth, nineteenth and twenty outputs of the first encoder are connected respectively to the subtracting, summing clock inputs and the reset input of the third reverse dd counter, the output of which is connected to the inputs of the seventh and eighth comparison blocks, the information input of the third register, the inputs of the fifth and sixth comparison blocks, the first The first information inputs of the first, third, and fourth comparison blocks are the inputs of the array end code of the third control block, whose information input is the input 50 into 1 of the second trigger and the information inputs of the second, fourth, and fifth registers, outputs The first and second blocks of comparison are connected to the first and second inputs of the equality signal of the first encoder, the inputs of the horizontal, frame sync pulse, whose clock input, the first information inputs of the fifth multiplexer and the second

the comparison unit and the second information input of the fourth comparison unit are the gate input of the third control block, the input of the ready signal of which is the input of the ready signal of the first encoder, the input of the input resolution of which and the input of the 1st third trigger are input of the input data enable signal of the third block control the second information inputs of the first comparison unit and the third multiplexer are connected to the output of the second register, the reset input of which, the reset inputs of the third, four The first and second registers are connected to the twenty first output of the first encoder, the twenty second output of which is connected to the control input of the second register, the third information input of the first comparison unit is connected to the twenty third output of the first encoder. from the twenty-fourth to the twenty-eighth of which the outputs are connected respectively to the recording control input of the fourth register, to the recording control input of the fifth register, to the third information input of the fourth comparator unit, to the second information input of the third comparator unit and to the installation input in O of the first trigger, the installation input in 1 of which is connected to the output of the fourth comparison unit, the second information inputs of the second comparison unit and the fifth multiplexer are connected to the output of the fourth register; the inputs of the third multiplexer and the third comparison unit are connected to the output of the fifth register, the fourth information input of the third multiplexer is connected to the logical zero bus, the third input the equality signal of the first encoder is connected to the first output of the third comparator unit, the second output of which is connected to the signal input More than the first encoder, the input of the signal-sign of the word is connected to the output of the sixth comparator unit, the direct and inverse outputs of the second trigger are connected respectively to the inputs of the recording signals and erasing the first encoder, the inputs of the signals of the signs of the zero and single address of which are connected to the outputs of the eighth and seventh comparison blocks, respectively, the forward and inverse outputs of the first The trigger of the trigger is respectively connected to the first and second inputs of the signal, the prize) aka the end of the memory area of the first encoder, the input signal of the sign of the end of which is erased is connected to the output of the fourth trigger, direct and

The inverse outputs of the third trigger are connected to the first and second inputs of the data modification solution of the first encoder, the input signal of the sign of the equality of the address of which is connected to the output of the second comparison unit.

 Ntam j

Phases. e / g (rvZH1GN1tet

(Naiala)

eleven-

vitm. LZag blue ",

 Ksshya and ahhh.

{StAZlUMSO

/ st TPaglshty4

tefiacvstno.

SftSf (feaar / t saKf)

Fzg, 6 b (ijpo3a / jxi

PhagSbModalkenae}

From the beginning 3

Ш1Т 1Ш шшш s {{woaseu.6iiif.i3,2lt

 plnao

aei / .CPYMtiYTtr KOH / afam.SS

-;

Sa / t.apapoat.CvK (caeiffiix.tB / MffSa I

Not

-diiH. "iapaia-C4SZ m sigi, tba 7 lUIHSO

8l;

FORN11 sagn. hu4MH80a ittunei

.1u I I I I

wcm cms Snix.

 CTM

Charmao.Sigk ifr03 / Z vxA MHSOuit / meSS

mt / iS 6 (eraser)

Claims (1)

Claim 1. A device for displaying information on a television indicator screen, comprising a buffer memory unit, first, second and third random access memory blocks, first and second control units, a first multiplexer, a register, a first and second shift register, a character generator, 21 second and second open and an address finder, the first and the moves of which are connected to the second address inputs of the third RAM blocks, the information inputs of which are connected to the output of the character generator, the first address input of which is connected to the output an register, the information input of which and the input of the sign code of the end 1 of the array of the first control unit are connected to the output of the first RAM block, the address and control inputs of which are connected respectively to the first and second outputs of the first control unit, the third and fourth outputs of which are connected respectively to the first information and the control inputs of the first multiplexer, the output of which is connected to the information input of the first block of RAM, the first output of the second control unit is connected to the control input of the buffer memory block, the information input of which is 25 information inputs of the device, the second output of the second control unit is connected to the reset input of the first register, the third output of the second control unit is connected to the control input 30 of the address generator, the clock input of the character generator is connected to the fourth by the output of the second control unit, the fifth output to the controllers of the second registers is connected to OR, the output of which is connected to the video input of a television indicator, the sync input of which is connected to the sixth output of the second control unit, the seventh output of which is connected to the gate input of the first control unit, the output of the second random access memory unit is connected to the first information inputs of the first and second shift registers, second information inputs which are connected to the output of the third block of RAM, different. ; the fact that, in order to improve the performance of the device, it contains a third control unit, a fourth RAM unit, a second multiplexer, write and read address counters, the outputs of which are connected respectively to the first and second information inputs of the second multiplexer, the output of which is connected to the sub-inputs of the first and shift, outputs by inputs of the element by the address input of the buffer memory unit, the output of which is connected to the information input of the address generator and to the second and third address inputs of the sign generator the radiator, the information inputs of the second and third control units and the information input of the write address counter are connected to the information input of the buffer memory unit, the first, second and third outputs of the third control unit are connected respectively to the information, address and control inputs of the fourth RAM unit, the output of which is connected to the second information input of the first multiplexer, and to the input of the code of the sign of the end of the array of the third control unit, the fourth output of which is connected to the input of the signal th the first control unit, the fifth output of which is connected to the input of the ready signal of the third control unit, the input of the data input enable signal, the control input of the second multiplexer and the write control input counter of the write address are connected to the first output of the second control unit, the eighth output of which is connected to the gate input the third control unit, the sixth output of the first control unit is connected to the write control input of the first register and to the write control input of the read address counter, nformatsionny input of which is connected to the output of the first block of memory, the clock input of the write address counter is connected to a seventh output 40 of the second alignment. the unit is equipped with a third treper2. The device according to claim 1, wherein the control unit comprises a second,. _g Tille, fourth and fifth registers 45 "necks, second and third down counters, a first, second, third, fourth, fifth, sixth, seventh, eighth comparison blocks, third, fourth and fifth multiplexers, the first, second, third and fourth flip-flops and a first encoder, the first and second outputs of which are connected to the control inputs of the third multiplexer, the first information input of which is connected to the output of the third register, the recording control input of which is connected to the third output of the first encoder, the fourth output of which is connected nen with the control input of the fifth multiplexer, the output of the third multiplexer is the first output of the third control unit, the second output of which is the outputs of the fourth and fifth multiplexers, the fifth output of the first encoder is connected to the control input of the fourth multiplexer and is the third output; e (third control unit, fourth whose output is the sixth and seventh outputs of the first encoder, the eighth, ninth, tenth and eleventh outputs of which are connected respectively with the summing one, I subtract general clock inputs, recording control input, and reset input; the first reversible counter, the output of which is connected to the information input of the second-20th reverse counter and to the first information input, of the fourth multiplexer, the second information input of which and the information input of the first reversible counter are connected to the output of the second reversible counter, summing and subtracting clock inputs, the recording control input and the reset input of which are connected respectively to the twelfth, trinadzate, fourteenth and fifteenth outputs of the first encoder, sixteenth the seventeenth outputs of which are connected respectively to the inputs of the installation at 0 and 1 of the fourth trigger, the eighteenth, nineteenth and twentieth outputs of the first encoder are connected respectively to the subtracting, summing clock inputs and reset input of the third reversible dd counter, the output of which is connected to the inputs of the seventh and eighth blocks comparison, the information input of the third register, the inputs of the fifth and sixth comparison blocks, the first information - 45 inputs of the first, third and fourth comparison blocks are the input , the sign code of the end of the array of the third control unit, the information input of which is the input of the 5Q installation in 1 of the second trigger and the information inputs of the second, fourth and fifth registers, the outputs of the fifth and first comparison blocks are connected to the first and second inputs of the equality signal $$ of the first encoder, the inputs of the horizontal, frame sync pulse, the clock input of which, the first information inputs of the fifth multiplexer and the second comparison unit and the second information input of the fourth comparison unit are gating in the course of the third control unit, the input of the ready signal of which is the input of the ready signal of the first encoder, the input of the input enable signal of which and the installation input into the third trigger are the input of the data input enable signal of the third control unit; the second information inputs of the first comparison unit and the third multiplexer are connected to the output of the second register, the reset input of which, the inputs of the reset of the third, fourth, fifth registers, the installation inputs at 0 of the second and third triggers are connected to the twenty-first the output of the first encoder, the twenty-second output of which is connected to the recording control input of the second register, the third information input of the first comparison unit is connected to the twenty-third output of the first encoder, from the twenty-fourth to twenty-eighth outputs of which are connected respectively to the recording control input of the fourth register, to : Ode of recording control of the fifth register, to the third information input of the fourth comparison unit, to the second information input of the third comparison unit and to the installation input at 0 the first trigger, the installation input 1 of which is connected to the output of the fourth comparison unit, the second information inputs of the second comparison unit and the fifth multiplexer are connected to the output of the fourth register, the third information inputs of the third multiplexer and the third comparison unit are connected to the output of the fifth register, the fourth information input of the third multiplexer connected to the bus logic zero, ^z third input signal equality first encoder connected to the first output of the third comparator unit, the second output of which о connected to the signal input More than the first encoder, the input of the signal-sign of the word of which is connected to the output of the sixth comparison unit, the direct and inverse outputs of the second trigger are connected respectively to the inputs of the recording and erasing signals of the first encoder, the inputs of the signal signals of the zero and unit addresses of which are connected to the outputs respectively, of the eighth and seventh comparison blocks, the direct and inverse outputs of the first trigger are connected respectively to the first and second inputs of the signal indicating the end of the memory zone of the first fratora, terminator erasing signal input coupled to the output of the fourth flip-flop, a direct and inverse outputs of the third flip-flop are connected to first and second input signals to enable modification of the data of the first encoder, the input signa la address equality sign is connected to the output of the second comparator unit. FIG. 2 Fig.Z Fia5 ζ Mouth) ------------> Pestles Huafa. 3MH80 .— 7 --- 1. η <SX> PH.cumVT03S2ua shiPLM80 smuyye Yoriyro6 & shesyagn№ yESh / evb, & а & 7U7M8Q komparat. Chesya.T16 s! T> __________ 68, <roriir GOT 5SS on fyx.iMnSOiiuiune 52 .— / D — 1 ---- | yit ”in whitefish. GOTs I shit52, s9ooos T7S \ yusigimya.27PLYAOO -! 2 G —- Maas Sch262 io sien sbM-UMShO I —_ „n — I ......... Removing whitefish PT with '1Ш5!, СЛ8сТ? Б Тн.тмоо ifyeuMUXMaoattH G3 ^. before fi ^ 7bc (Kmett) Fiz. 6a (read mode) OaSSIeexuH sooocs) Toyot \ ChetSidZpo Si 62 by Uvgi. Vya.VshvO yiA.Cu62no siz "\ bykh.ashvo Twisted ev. from Sch5V, VZ Fkneigisht. 35 (Beginning) <i wk TZvieg tires V4 SHREVvashvVVm urgy.bykhTsMNvO yisie 80.51 tires V5 sosigigOvy · 23,2В LLI80 yzEl — kyabi.sr '/ and outng [koimrash-VV Etnir.sigi CT0352, \ Cfaic TTL whitefish. Out Huhtt 1-.:.-. .j ------ ^ hovZya> 1a.ecv2 wigg.Out. <ЗМН80 - <в_J -—_____ .27 - '^' ^ .KGI’P There is no £ ΞΞ sJIa \ Ust. S "vgpoSchdZ t UsigiVyhLMVO -------------- t, '| - 22edizM2 of the correct HMMVO ______, - 30 - ifrT — r tz52, ЗПрг! 0т> \ Signal OX1X.2 PNM80 AZ -... <... А ........ ЗП0392. Dan SRG 59 Jer & 's “G —p UtSchVZtSchdRtia WCHZMMvO „33 — Л— ~., ..., ____7_____i_ * £ dshkirash. whitefish. 1,770,392 at £ 56 £ »£ 719 With 18 resp. Figb δ (Herodalysis) 470352 sigi w No. f55itta> eii & 2tl№i —-27 I --- mM'jieuaPJXSSnacim. (ylZYN8vD1Yu352lery hee. NiHyusign.yykhl MM80 —28 --- ¹ ------- 3.dsh.prash..chch5253sia dsh.mShNvO.eda. Uneeyyi.Suds sigi. YYH.17 YLN80 UZsheydddZugierez Ht! X6Sna Signal Byh. stupidly (Kyeg.) —B- .. .1 .......- ....... Foriir whitefish. 470352 ив Exit and at step ВВ. — S С. . ~~ No. T7Sno blue. Out j lousy — 10 · у у г 'Ύ ~ Form up. whitefish. 070392 Exit in IL® and SB bus Fig. BCre> * in erase ^ \ Edinaris. Schb & L · fax. (in MM 80 r ~ —21—— Lardl schh / roz-SchM Fig B 6 (continue} (Pug 1. 1522272 "Βί'ί