SU1322320A1 - Device for processing video information - Google Patents

Abstract

The invention relates to computing. The aim of the invention is to improve the noise immunity of the display of information. The device contains a memory block 1, analogue-digital conversion BLS1, switch 3, register 4, clock generation unit 5, decoder 6, address generation unit 7, selector 8, clock generator 9, digital video signal generation unit 10, buffer memory block 11 , display unit 12, interrupt generation unit 13, AND elements 14.15, OR-NOT 16 element, register 17. 1 Cp f-ly, 7 ill. (С (/: с кте lAw - Uch7 eCfiitc, Ks4l

Description

one

The invention relates to computing and can be used in remote sensing of the Earth’s natural resources, in geology, medicine, and in non-destructive quality control of products.

The purpose of the invention is to improve the physical stability of the display of video information.

Figure 1 shows the functional diagram of the device; Fig. 2 is a schematic diagram of a memory block; in FIG. 3 — fuickz Yunapn — a digital-to-analogue conversion block diagram — in FIG. A — timing diagrams of work in reading information and in a batching mode); IN; with the help of the extras I and in FIG. 3 - the prince of the interrupt block diagram;

on (|) ig.6 - timing charts

block interrupt}; in fig. 7 is a functional block diagram of the address form.

The device contains a block of memory 1 block 2 analog-digital conversion, switch 3, register 4, block 5 of the formation of clock pulses, dei1frator 6, block 7 of the form-iKiiniH address, selector 8, sync generator 9, block 10 of the formation of digital-poBiiix-video signals , 11 buffer, display block 12, block 13 (1) is created .1 interrupts, eiemepty 51 14 and 15, element NLI-NOT 16 register 17, mul1 / 1 I1loxo 18, element MPiiTi i 19 memory, ke a) mmu 1 a; Op 20 analogue G opmh signals, portable digital I1) azozer (LII) 21, switchboard 22; d,) ormag ,, nodes 23–25 sprinkling; , element OR 26, trigger 27, element NOT 28, element I - PE 29, h rigger 30, elekt.1ent AND-NOT 31 counters 32-35 koo;) Dinat, address setting node 36, trigger 37, element OR 38 , elements And 39 and 40, switch 41, resistor 42, capacitor 43. I

IjjioK 10 consists, for example, of a color-coding node, a label formatting node and three digital-to-analogue converters. The operation of the color-coding node is based on comparing the current digital video e; 1gval, coming from the output of block 11 with M subgroups AND levels, in converting the output code of the comparison circuit with the help of the encoder into three central | 1-e video signals with the subsequent

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conversion of these signals into three analog video signals, which are fed to the corresponding inputs of block 12.

The color scale generation unit forms in the lower part of the screen of block 12 a color coding law. The digital signature generator also forms the right-hand part of the screen with the threshold level values specified in the color-coding scheme. The tag generation unit forms on the screen of block 12 a label in the form of a flashing dot that moves the marrow. The value of the information stored in the cell of the memory block 1, having the address corresponding to the coordinates of the label, is output via the digital generator to the screen of the block 12.

ten

15

O block

five

0

five

0

five

0

five

performed on parallel-shift shift registers; parallel recording and shifting of information is carried out on the negative edge of TI, and the choice of mode (parallel recording or shifting) is determined by the signal at the control input.

Block 12 is, for example, a standard device of the type VK51TS61, VK59T60, VKAOTsO, with which the country's television centers are equipped, or a special manitor. Incoming, for example, in a computer Electronics-85.

Block 13 is designed to allocate a full cycle when asynchronously accessing block 1 of memory from external devices. A schematic diagram for generating pulses corresponding to a cycle of circulation from one of the external sources is shown in FIG. 3, and the timing diagrams of the operation of this circuit are shown in FIG. 6. The control signal (Fig. 6g) is supplied from one of the external sources to the inputs 1,3 and A, by which the cycle is selected. Fig. 6 shows the control signal on the second input of the block 13, and Fig. 6 shows the boundaries of the cycles to access the memory block 1. The control signal coming from one of the external sources (fig.6g) is fed to the installation input of the trigger 27 and sets it up (fig.6).

The signal from the output of the trigger 27 permits the passage of the inverted signal (FIG. B) through the element IS-NOT 29 (FIG. 6 e). The signal from the output of this element enters the counting

31

the trigger input 30 and switches it to a positive differential (fig.bzh). On the NAND 31 element, a pulse shaper is produced from positive drops at the inverse output of the trigger 30 (Fig. 6 J). This pulse resets the triggers 27 and 30 to the initial state and stops the block before the next trigger pulse arrives. The same impulse from the output of the nodes 24 and 25 through the OR element 26 is a signal that indicates the end of the circulation cycle when working with a computer.

The selector 8 contains XI and FID selection nodes that are extracted from the output video signal, XI and FID delay nodes, XI drivers, (output 1) and FID (output 2), the sync pulses from the outputs are delayed until the active part of the frame is started at the source TV video signal, fake pulse former and fixer 1 & SC. (exit 3).

The clock generator 9, for example, contains a generator TI, depot, delay elements, drivers, elements OR. Sync generator 9 ejects full BSC sync signal (output 4) according to GOST, TI (output 3) -. lowercase FID (output 2) and frame XSI (exit 1), delayed until the active part of the frame is displayed on the screen of the video monitoring unit.

The device works in the following way.

The main mode of operation is the readout mode of a digital signal from memory block 1. Information is read during the forward run of the sweeps of block 12. Memory block 1 is organized, for example, 256x256x8 bits. Since the scanning time of a single element of the television image with a square raster and the number of active pixels of 256x256 is 140 NS, and the minimum read / write cycle time for memory elements is 510, the circuit implements the principle of parallel-serial reading of information. For this purpose, the duration of the memory access cycle is chosen such that during this time 2N image elements are displayed on the screen.

wives }) and FIG. 4 shows the time diagrams (for) of the main control address signals when the system is operating in the mode of reading information from memory block 1. The pulses from the second output of the sync generator 9 (Fig. 4a) are line sync pulses delayed with respect to the synchronization pulses of block 12. The delay is introduced in order to read information from memory 1 during the forward run of block 12.

The pulses from the third output of the clock generator 9 (Fig. 4B) have a period equal to the duration of one element of the television image. The pulses of the second spin of the clock 9 synchronize the operation of block 5,

and the pulses of the first and second outputs of the synchro-generator 9 - the operation of block 7, the signal diagrams at the outputs 1-4 of block 5 are shown in FIG. 4 & 4, e. Counter - (Yurmi is the address organizer for the X coordinate. It starts at the beginning

the active part of each ;; th line and changes its state by 1 with the arrival of the next clock pulse. Chart Signals Chthaphone Junior

bits are shown in figure 4, l, and, k. The counter is (address shaper by coordinate Y, resets at the beginning of the active part of each frame and changes its state to 1 with the arrival of the next sync pulse.

Output bits X ,, and Y ,,, through the switch of block 7 are fed to the outputs of block 7, and the second output of block 7 receives -fi junior

bit d X, and on the first exit - senior bits X, and bits U. Besides

This, at the fifth output of block 7, by the minute switch, the signal of the N + 1-th bit is received (FIG. 4P). In scramble mode

information on the screen of the block 12, the information of each bit of the memory block 1 is read simultaneously from

 .

2 +1 memory chips and at the end of the read cycle is fixed by a positive signal edge from the fourth I

output of block 5 (Fig. 4e) in register 17. At the end of each second cycle, information from register 17 on the negative edge of the TI and the control signal from the output of the AND unit 15 (Fig. 4 l) is rewritten into block 11 and with the same TI in a sequential manner is output to block 10.

At the end of each 1-second memory access cycle in read mode, the ct-teha address at the address output of block 7 (FIG. 4K) occurs and the process of reading information is repeated at the new address. In the work mode With external devices, similar to the read mode, it is necessary to form the address signals X and the corresponding source. These signals are formed in block 7 by counting TI, SSID ,, XI for small-frame systems and using the calculation of TI. |, And XI.ts for television systems. Simultaneously with the formation of the current TI address of one of these advanced devices, the launch of the LCP 21 of block 2, the input of which receives an analogue signal, is sent to the corresponding external source. But around the conversion of the a1 signal to the digital signal in block 2, a signal is generated at the end of the conversion, which falls on the first input of the interrupt block 13. On the first output of interrupt unit 13 (a signal is generated which, at the time of accessing the memory, connects to the first and second outputs of block 7, address signals Xjr, n Yj, from the corresponding source,, to -r to nn j) L) pManMoiiHON y Bfjxo; iy blockch 2 output LUP and generates a recording signal at one output, p, s decoder 6. Record: D) information and a cell of memory 1 unit .1ms1 |; according to the 1: ction element of the signal memory; about a record, the ilocjje of this device goes into a mode called and the formation on the screen of the block 12. Operation. С1 of the system 1 mode exchanging information with the electronic IU Bgp1sliteolnoy nashi- Hoii (computer) does not differ from that described mode.

In the mode of recording information from the computer i, the device (control: P1y signal on cn; -th input of block 13) addresses and data come directly from the computer and are connected by the switch of block 7 to the inputs of block I of memory to the inputs of the decoder by controlling the sigpal with the second output of block 13. In the mode of reading information from the device to the computer (control signal at the fourth input of block 13), the address is received and the signal comes directly from the computer and through the switch of block 7 is connected to the inputs

five

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the memory unit 1 and the inputs of the switch 3 using the signal from the output of the unit 13, in addition, the trailing edge of this signal information is recorded in register 4 and enters the computer. In this case, the signal WE is not generated. Thus, in the external device operation mode, one of the cycles of accessing the memory unit 1 is used to write (read) information from this external device. From the point of view; two readings are possible. interrupt occurrence: an interrupt occurs during the first cycle of accessing memory block 1 after changing the address, at the first address output of block 7, the interruption occurs in the second cycle after changing the address at the first address output of block 7.

Fig. 4m shows a pulse at one of the outputs of block 13, corresponding to the first cycle of accessing memory block 1 from an external device, after changing the address at the first address output of block 7. In this cycle, the signal to the register entry 17 does not come (Fig. 4h), and the information in this register appears at the end of the next cycle. But the access to the memory block in the next cycle goes to the same address and in the register 17 at the end of the next cycle, the information that should be displayed on the screen of block 2,

Fig. 4a shows a pulse on one of the outputs of block 13, corresponding to the second cycle of accessing memory block 1, after changing the address at the first address output of block 7. In this cycle, the signal to the input of register 17 does not arrive (Fig. 4 d) and therefore it stores information recorded in the previous reference cycle, which passes to the same address.

Thus, in this case, in block 11, at the end of this cycle, the information that is currently displayed and should be displayed on the screen will be overwritten. Thus, regardless of which of the cycles interrupts occur, the information on the screen of block 12 is reproduced without distortion.

When the device operates in the mode of information exchange with external devices on the screen of unit 12, no impulse noise appears on the image. The absence of interference improves the quality and improves the conditions for the perception of video information by the operator, which allows the operator to conduct visual 5 analysis of the displayed information in parallel with the processing of this information using a computer. This leads to a decrease in operator fatigue and increased 3223208

with the clock pulse output of the sine generator, with the first information input of the clock pulse shaping unit and with the clock inputs of the buffer memory block and the digital video signal shaping unit, the output of the frame clock pulses is connected to the first information input of the digital video signal forming unit whose second information input and The second information input of the clock shaping unit is connected to the output of the horizontal sync im1. A device for processing video, 5 pulses of the synchro-generator, the outputs of the forming unit 1 of the 1-D video signals are connected respectively to the information inputs of the display unit, and the third information input

formational output of the memory block pod-l with l. . Q 1Q 1l, 20 is connected to the output of the buffer block, eventually, labor productivity.

Claims (2)

Invention Formula the information containing the memory block, the information input of which is connected to the information output of the analog-to-digital conversion unit, in10 Key to the information input of the switch, the output of which is connected to the information input of the first register; The first to third synchronization inputs of the memory block are connected respectively to the first through the third outputs of the clock generation unit; the write inputs of the memory block are connected to the decoder outputs, which synchronize the input of which is connected to the third output of the block forming the clock impulses30 The sync input of the display unit is connected to the output of the display control of the synchronous generator, the first control output of the interrupt generator is connected to the first control of the decoder, the address generation unit and the analog-digital conversion unit, the second control the 1st output of the interrupt generator is connected to to the second control inputs for the decoder of the address generation unit and the analog-to-digital conversion unit, the third control output is connected ow, the address input of the memory unit is connected to the first address output of the address generation unit, the second address output of which is connected to the address input of the switch and the information input of the decoder, the first and second control outputs of the unit are formed1-; the addresses are connected respectively to the first and second control drives of the analog-digital conversion unit, the frame sync input and the horizontal sync pulse of the address generation unit are connected respectively to the frame sync output and the horizontal sync pulse of the selector, the information output of which is connected to the first information input of the analog block digital conversion, the first and second installation inputs of the address generation unit are connected respectively to the personnel blue outputs drivers has a synchronizing pulses and horizontal synchronizing pulses sinhrgeneratora, first information input address generating unit soedi10 five 0 The sync input of the display unit is connected to the output of the display control of the synchronous generator, the first control output of the interrupt generator is connected to the first control of the decoder, the address generation unit and the analog-digital conversion unit, the second control the 1st output of the interrupt generator is connected to to the second control inputs for the decoder of the address generation unit and the analog-to-digital conversion unit, the third control output is connected 5 to the input of the first register and to the third control input of the address generation unit; the first control input of the interrupt generation unit is connected to the output of the feature 0, the conversion of the analog-to-digital conversion unit, the sync input is connected to the second output of the clock generation unit, the second and third information The 5 input inputs of the analog to digital conversion unit are the first and second information inputs of the device, the third information input of which is connected to the second information input of the address generation unit, the fourth information input connected to the information input of the selector, the first and second installation inputs five the devices are connected to the third and fourth installation inputs of the address generation unit, the address input of which is the address input of the device 9 The output of the first register is the information output of the device, the output of the read signal of the interrupt generating unit is the output of the read attribute of the device, the first and second information inputs of the interrupt generating unit are respectively the fifth and sixth information inputs of the device, different from. By the fact that, in order to improve the noise immunity of the video information display, a second register, two AND elements and a 1CHI-NOT element are entered into it, the information input of the second register is connected to the information output of the memory block, and the information output is connected to the information input of the buffer memory block , the outputs nepBoi o and the second element I are connected respectively to the recording inputs of the second register and the buffer memory block, the first input of the second element H is connected to the third control output of the control unit, the first input of the first element AND and the second input of the second element AND are connected to the fourth output of the block (clock generation, nepDbiii, the second and third controls the outputs of the interrupt shaping unit are connected respectively to the inputs of the OR-NOT element, the output of which is connected to the second input of the first I. - 2. The device according to claim 1, which is based on the fact that the address generation unit contains four coordinate counters, an address setting node, a trigger, a scientific research institute element, two AND elements and a switch, whose outputs are the first and second address output of the block, information inputs of the switch are connected to Responsibly, with the outputs of the bits of the first OR control, the second control, second, third, and fourth, output of the block. fO 20 2232010 coordinate counters, with information upper; address node node and address block input, the first information input of the block is connected to the count input of the first coordinate counter, the trigger reset input and the first input of the OR element, the setup input of the second coordinate counter is the first installation the input of the block, the second installation input of which is connected to the installation input of the first coordinate counter and to the counting input of the second coordinate counter, the second information input of the block is connected to the counting input ter its coordinate counter, the installation input of the fourth coordinate counter is the third installation input of the block, the fourth installation input of which is connected to the installation input of the third coordinate counter and to the counting input of the fourth coordinate counter, the third discharge output of the first coordinate counter is the third control output the block, the inputs of the address setting node are respectively the inputs of the line sync pulse and frame sync pulse 30 node for specifying an address, the output of the sign of which is connected to the second input of the OR element and to the input of the trigger setup, the direct output of which is connected to the first control output of the block 35 and the first input of the first element I, the zero output of the trigger is connected to the first input of the second element I, the second inputs of the first and second elements I are connected to the first control input of the unit, the control inputs of the switch are connected respectively to the outputs of the first and second elements I and I with the second and third control inputs of the block, the alea output h Jlj1JlЛJlJlJUlЛJlЛJгпJгглл e well 3 and d lm n o p P 2 j Fig.Z P J J t t t Л .t FIG. FIG. five r i Editor N.Rogulich Compiled by A. Zherenov Tehred L. Oliynyk Proofreader G. Reshetnik Order 2867/47 Circulation 672 Subscription VNIISH1 USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab, d. 4/5 Production and printing company, Uzhgorod, st. Project, 4