SU1587482A1 - Device for output of graphical information on screen of television in indicator - Google Patents

Abstract

The invention relates to automation and computing and can be used to display the form of the signal under study in radio measuring devices controlled by a microprocessor. The purpose of the invention is to increase the speed of the device. For this purpose, a code converter and a switch 12 are inserted into the device with corresponding functional connections. This allows the use of a regeneration memory with arbitrary organization, which ultimately improves performance. 3 ill., 1 tab.

Description

The invention relates to automation and computing and can be used to display the form of the test signal in radio measuring devices controlled by a microprocessor.

The purpose of the invention is to increase the speed of the device.

FIG. 1 and 2 shows a block diagram of the device; But FIG. 3 - various versions of the block diagram of the code converter.

In tab. Tables 1 and 2 show the coding for the highest and lowest tetrads, respectively.

The device contains 1 control, register 2 X coordinates, register 3 Y coordinates, multiplexer 4, regeneration memory block 5, input register 6, output register 7, shift register 8, synchronization block 9, television indicator 10, code converter 11, switch 12.

Control unit 1 contains address selectors 13 and 14, analog-to-digital converter 15, main memory unit 16, CONSTANT memory unit 17, microprocessor 18, system controller 19, control register 20, buffer register 21, fixed memory block 22, register 23, constant memory block 24.

 The regeneration memory block 5 contains memory blocks 25 and 26, a buffer 27, a multiplexer 28.

The synchronization unit 9 comprises a clock pulse generator 29, counters 30 and 31, a pulse driver 32.

The television indicator includes a video multiplier 33, a sweep generator 34, a cathode ray tube (CRT) 35.

The device works as follows.

The control unit 1 generates control signals determining the cycle of operation of the device, which consists of two intervals: a display interval of information that takes place continuously during the forward stroke of the horizontal and vertical scanning and inter (L

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an information change shaft in block 5, which is programmed as needed.

In the information display interval, the synchronization unit 9 accesses the regeneration memory block 5 in order to read the next information word, which in the next cycle is displayed on the screen of the CRT 35. The read information is entered into the shift register 8, which is converted into a sequence of video signals the video input of the indicator 10. By the time when the information of the register 8 is sequentially converted into video signals by the synchronization unit 9, the following is prepared together with the control unit 1 ovo zanosits information and a shift register 8, thereby forming a contiguous sequence of video signals during the forward stroke of scans. At the inputs of the television indicator 10, in addition to the sequence of video signals, the sync signals of vertical and horizontal sweeps from block 9 are received.

The word conversion time of the information into a sequence of video signals is much longer than the required time to prepare the next word, and therefore the rest of the display cycle time is allotted for the microprocessor 18 to access the regeneration memory block 5. Blocks 20-24 constitute a firmware control device which, together with the signals of synchronization block 9, provides for performing the following operations: writing a byte to block 5 of the regeneration memory, reading a byte of information from block 5 of the regeneration memory, setting a specific bit in a byte, clearing a certain bit in byte.

The microprocessor 18 processes the information contained in blocks 16 and 17 and prepares the data necessary to perform the above operations on memory block 5. When writing a byte by the microprocessor 18, the following actions are performed; the byte address is written to the address registers 2 and 3 via the data bus, the data is entered into the input register 6 via the data bus, and the code of the write operation to the control register 20 is set.

The contents of input register 6 are transmitted through a converter 11 of a code to an in-. The formation inputs of the memory block 5 are located at the address determined by the contents of registers 2 and 3 in the time interval intended for servicing the calls of the microprocessor 18. At the end of the indicated interval, the control register 20 is reset. The execution time of a byte write operation is usually equal to half the time of one display cycle.

When reading a byte of information from the block

5 memory software performs the following actions: write the byte address to registers 2 and 3, set the read code to control register 20, read 0 byte from output register 7 to microprocessor 18 via the data bus.

At the end of the reading interval, as in the case of other operations, the control register 20 returns to the initial state. 5 read and write operations can be used, for example, to perform online testing of memory block 5.

The following actions are performed to perform the bit setting operation by the microprocessor: writing the bit address defined by the X and Y coordinates of the display element to registers 2 and 3, setting the bit setting operation code to the control register 20.

5After receiving the specified opcode, the current or next display cycle reads from block 5 byte of information, which contains the specified bit, writes to output register 7, 0 sends the code to the input of the code converter 11, and executes the last byte processing of setting to one bit defined by the lower bits of the X coordinate РХ2 ... РХО, the transmission to the information-5 inputs of block 5 and the entry of the processed byte to the specified address, i.e. in this case, a read-modify-write loop is performed. In this case, the byte address is defined as the concatenation of the contents of register 3 and the high part of register 2, the minor part of the X coordinate РХ2 ... РХО determines the bit number in a byte. This operation is performed at time intervals intended for servicing the calls of the microprocessor 18, after which the initial state of the control register 20 is set.

To perform a bit-clearing operation by a microprocessor, actions similar to the bit-setting operation are performed, except that the bit-clearing code is entered into control register 20.

Further, the same operations are performed as with the bit installation. The difference is. that the code converter 11, under the control of the signals of block 1, clears the bit in the byte defined by the coordinates РХ2 ... РХО.

Blocks 16. and 17 store one or more arrays of information (for example, a digital signal of 256 samples and borrowing 256 bytes) that are currently displayed on the CRT screen. If you need to change one of the displayed graphs, you must perform a sequence of cleaning operations and setting bits.

The code converter 11 transfers the contents of the output register or the input register to the information inputs of block 5, setting a bit or clearing specified by the РХ2 ... РХО coordinate, controlled by signals К1, КО of block 1. Several embodiments of the converter are shown in Fig. 3.

To get the most senior (Table 1) and the lowest (Table 2) tetrad code converter (Fig. 36), the following actions are performed: with the control code K1, (clearing the bit) the specified bit is set to the zero state, the rest are transmitted to the output in unchanged state; with code K1, (setting the bit) the specified bit is set to one, the rest are transmitted to the output in the same state; with code K1, information is transmitted to the output without modification.

Thus, the introduction of the code converter 11, the switch 12 and the corresponding functional links allows the use of the regeneration memory block 5 with arbitrary organization and increase the speed of the device.

Claims (1)

Invention Formula A device for displaying graphic information on a television indicator screen comprising a control unit, registers of X coordinate and Y coordinate, input register, output register, shift register, multiplexer, regeneration memory block, synchronization block, the first and second outputs of which are connected respectively to the frame and horizontal synchronous inputs of the television indicator, the video input of which is connected to the output of the shift register, whose information inputs are connected to the outputs of the regeneration memory block connected to the information and the inputs of the output register, whose recording control input coupled to the first output of the control unit, data inputs and outputs of which are connected to the data inputs of the coordinate registers X and Y and an input register, input recording control of which is connected to the second output of the control unit, the third and fourth outputs of which are connected respectively to the recording control inputs of the coordinate registers X and Y, output The register of the Y coordinate and the first output of the register of the X coordinate are connected to the first information input of the multiplexer. The second information input of which is connected to the third output of the synchronization unit, the fourth output of which is connected to the clock inputs of the shift register and the control unit, the fifth output of which is connected to the control input of the multiplexer, the output of which is connected to the address inputs of the regeneration memory block, the sixth output of the control unit connected to the write control input of the shift register, the seventh output of the control unit is connected to the read control inputs input and output registers, the first address input of the control unit is connected to the fifth output of the synchronization unit, the sixth output of which is connected to the synchronous input of the control unit, the information input which is an information input device, characterized in that. that, in order to increase the speed of the device, it contains a code converter, a switch, the outputs of which are connected to the information inputs / outputs of the control unit, the outputs of the first group of which are connected to the control inputs of the regeneration memory block, with the information inputs of the code converter group, the first information input of which is connected to the outputs of input and output registers, the second output of the X coordinate register is connected to the second information input of the code converter, the output of which is connected to the information input of the regeneration memory block, the control input of the code converter is connected to the eighth output of the control unit. the second address input of which is connected to the multiplexer output, the information input of the switch is connected to the output of the output register, the control input of the switch is connected to the ninth control unit output. Table 1 table 2 Th g r I g ; Y J LG2..Lee AMlMW Control nt.nt t