SU1399811A1 - Device for output of graphic information - Google Patents

Abstract

The invention relates to computing and automation and can be used by Cpus.l to display graphical information in design automation systems and in the processing of graphic data. The purpose of the invention is to increase the speed of the device - by introducing registers 19, 20, 21, comparison blocks 23-26f of triggers 27, 30, counter 31, elements And 28, 29, 32, and corresponding functional connections. The invention allows for the programming of the size and displacement of the image displayed on the screen, thereby increasing the effective performance of the computer due to the reduction in the time spent on accessing the computer memory. 2 Il. (L with f t: D; o eo

Description

The invention relates to computing and automation and can be used to display graphic information in design automation systems and in solving problems of processing graphic data.

The purpose of the invention is to increase the speed of the device.

Figure 1 presents the block diagram of the device; Fig. 2 is a view of a displayed image on a television indicator screen.

The device contains a generator of 1 pulses, a counter of 2 points, a counter of 3 lines, the first 4 and second 5 decoders, shift register 6, the first element And 7, the first trigger 8, the first adder 9, the second 10, the third 11, four 12, n Tash 13 triggers, TV indicator 1A, element group I 15, first counter 16 and puls, second adder 17, address register- 18, first 19, second 20, third 21, quarter 22 registers, first 23, second 2A, third blocks comparing the sixth trigger 27, the second element And 28, the third element And 29, the seventh trigger 30, the second counter 31 pulses, quarter ь element and 32.

The device works as follows.

The generator 1 of the pulses generates high-frequency pulses corresponding to the required screen raster sampling horizontally, which is fed to the input of the 2-point counter and the synchronization input of the shift register 6, shifting the information contained in it, which is stored from the computer memory. The capacity of the shift register 6 is equal to the memory word width. The recalculation coefficient of the 2-point counter corresponds to the TV standard of the horizontal scan length. The signal from the high-order output of the 2-point counter enters the input of a 3-line counter, which recalculates image lines in a frame and has a recalculation period corresponding to the length of the vertical scan. t

Signals from the counter code 2 points

and the counter of 3 lines is fed to the input of the first A and the second 5 decoders.

The first 4 decoder generates control signals to write the information word to the shift register 6, flip the first trigger 8, which allows the video signal from the shift register 6 to pass through the first element 7 during the visible run from the frame and horizontal sweeps, and the horizontal pulse forming signals, formed by the second trigger 10, the pulse of the lower-end zero-band, formed by the third trigger 11, the frame pulse, forwarded by the fourth trigger 12, the pulse of the personnel protective strip, generated by trigger 13.

The components of the television synchro mix obtained in this way, together with the video signal coming from the output of the first element And 7, are converted by the first adder of a 9 l standard television video signal,

0 which enters the video input of the television indicator 14. Signals from the output of the second depggator of 5 are fed to the elements AND groups, which, together with the signal, r-n1 from the code third of its 11 and a sign of the 13 trigger signals from Computer, and the request for the next memory word is combined in time with the shift of the previous word and the register.

Nzch; Glpt address L vylod mogo on the array screen is entered from the computer in the registrar 18 addresses. In the first register 19 of the computer, the size 2 is horizontally entered into the image of the computer. In the third register 21 of

The computer is scrolled to a size of 2 images displayed on the screen in rows. In the second register 20 is entered

0 the value of K is the displacement in words of the displayed image relative to the left side of the screen, and in the fourth register 22 - the value of K ,, the displacement in the lines of the displayed image relative to

5 of the upper edge of the screen in accordance with FIG. At the same time, the maximum possible information capacity of the screen is 2 ° bits horizontally and 2 lines vertically, and the word width of a computer is 2 bits.

The code K ,, recorded in the second register 20, is compared in the second comparison block 24 with the code at the outputs of the 2 point counter. When a code coincides at the output of the counter 2 points with K at the output of the second comparison unit 24, an impulse appears that sets to 1 sixth trigger 27. Similarly, the outputs of the 3-line counter

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compared with K. in the third block of comparison 25 and when a pulse coincides with its output, it is set to 1 seventh trigger 30. Conjunct1 outputs of the sixth 27 and seventh 30 triggers on the third element And 29 allow the passage of pulses of addition 1 to the address from the counter of 2 points through the fourth the element 32 and the passage of the signals of the temporary memory diagram, the passage of the search through the group of elements 15 and 15.

The first 16 and second 31 pulse counters form an address counter, the first 16 counter having (a-p) binary bits, and the second counter 31 — b binary bits.

The outputs of the first 16 and second 31 counters, arriving at the first inputs of the second cyTff-iaTopa 17, form the OT i-address of the readable slots. The second adder 17 accomplishes the formation of the absolute address of the word being read by adding A to the relative address. In addition, the address signals of the first 16 and second 31 counters are received respectively at the second inputs of the first 23 and fourth 26 comparison blocks, where they are compared with 2 and 2, the size of the image is determined. When the output code of the first counter 16 coincides with 2, a pulse is formed at the output of the first block of comparison 23, setting sixth trigger 27 and first counter 16 to O. This same pulse, passing through the second element 28 and opening the output of the seventh trigger 30,

steps onto the counting input of the second counter 31 and adds one to its contents. When the code in the second counter 31 coincides with 2 at the Output of the fourth comparison unit, a pulse is generated, which resets the seventh trigger 30 and the second counter 31.

In the next frame, the 1st set up and reset of the sixth 27th and seventh triggers is repeated from the beginning.

Thus, due to the programmability of the dimensions and the displacement of the image displayed on the screen, the productivity of the computer is increased by reducing the time the device accesses the computer memory.

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A device for outputting graphical information containing a pulse generator, point counter, row counter, first and second decoders, first, second, third, fourth and fifth triggers, shift register, first element I, first adder, television indicator, group of elements And, the first pulse counter, the address register, the second adder, the output of the generator and mylcov are connected to the counting input of the point counter, the first output of which is connected to the counting input of the row counter, the second output of the counter i; a points I go to the first and second inputs It is connected to the second input of the first decoder, the first output of which is connected to the control input of the shift register, the sync input of which is connected to the output of the generator and the radio, the information inputs of the shift register are the input inputs of the device, the output of the shift register with Pernd input of the first element And, the second input of which is connected to the output of the first trigger, the output of the first element And is connected to the first information input of the adder, second, third, h The fourth and fifth information inputs of the first adder are connected to the outputs of the second, third, fourth, and fifth triggers, the inputs of the first, second, third, fourth, and fifth triggers are connected to the second, third, fourth, fifth, and sixth outputs of the first decoder, output The first adder is connected to the video input of the television indicator, the outputs of the second decoder are connected to the first inputs of the elements AND groups, the second inputs of which are connected to the outputs of the third trigger, and the third inputs to the output of the fifth trigger, outputs The elements and groups are the control outputs of the device, the output of the first pulse counter is connected to the first input of the second adder, the second input of which is connected to the output of the address register, whose information input is the address input of the device, and the control input is the first control input of the device The outputs of the second adder are address outputs of the device.

It is different from the fact that, in order to increase the speed of the device, it contains the first, second, third and fourth data registers, the first, second, third and fourth comparison blocks, the sixth and seventh triggers, the second pulse counter, the second, third and The fourth And elements, the outputs of the first, second, third, and fourth data registers are connected to the first inputs of the first, second, third, and fourth comparison blocks. The information inputs of the data registers are the first, second, third, and fourth control inputs of the device. The two control inputs of the first and fourth data registers are the second and third control inputs of the device; the control inputs of the second and third data registers are the fourth control input of the device; the second input of the first comparison unit is connected to the output of the first pulse counter; the output of the first block Comparison is connected to the inputs. Setting the zero of the first pulse counter and the sixth trigger and the first input of the second element, And the second input of the second comparison block is connected to the third output of the point counter, and you od

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setting the unit of the sixth trigger, the output of which is connected to the first input of the third element, the second input of the third comparison unit is connected to the second output of the row counter, and the output of the third comparison unit is connected to the input setting the unit of the seventh trigger, the second input of the fourth the comparison unit is connected to the output of the second pulse counter and to the third input of the second adder, the output of the fourth block is compared to 15 NINs connected to the inputs. Setting the zero of the seventh trigger and the second counter and pulses, the seventh output

trigger is connected to the second input of the third element And whose output is connected to the first input of the fourth element And, the second input of which is connected to the fourth output of the point counter, the output of the fourth element And connected to the counting input of the first pulse counter, the output of the third And connected to the fourth inputs of the elements H group, the second input of the second element And is connected to the output of the seventh trigger, the output of the second element And is connected to the counting input of the second counter im1 pulses.

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Claims (1)

The formula is invented and ~ I The first 16 and second 31 pulse counters form an address counter, the first 16 counter having (a-p) binary digits, and the second counter 31 having b binary digits. The outputs of the first 16 and second 31 counters, arriving at the first inputs of the second cyifMaTopa 17, form the relative address of the read word. The second adder 17 generates the absolute address of the read word by adding A _p to the relative address. In addition, the address outputs of the first 16 and second 31 counters are respectively supplied to the second inputs of the first 23 and fourth 26 comparison units, where they are compared with 2 ^P and 2 ^Gp , which specify the image size. When the output code of the first counter 16 with 2 ^P matches, the output of the first comparison unit 23 generates a pulse that sets the sixth trigger 27 and the first counter 16. The same pulse, passing through the second element And 28, opened by the output of the seventh trigger 30, is fed to the counting the input of the second counter 31 and adds one to its contents. When the code coincides in the second counter 31 with 2 ^01, an output is generated at the output of the fourth comparison unit, which resets the seventh trigger 30 and the second counter 31 to 0. In the next frame, the installation and reset cycle of the sixth 27th and seventh triggers is repeated first due to the offset program. Thus, by increasing the size of the image on the image screen, computer performance is improved by reducing the time the device accesses the computer memory. A device for outputting graphic information containing a pulse generator, point counter, line counter, first and second decoders, first, second, third, fourth and fifth triggers, shift register, first element And, first adder, television indicator, group of elements And, first pulse counter, address register, second adder, the output of the pulse generator is connected to the counting input of the point counter, the first output of which is connected to the counting input of the line counter, the second output of the point counter is connected to the inputs of the first and second of decoders, the first output of the line counter is connected to the second input of the first decoder, the first output of which is connected to the control input of the shift register, the clock input of which is connected to the output of the pulse generator, the information inputs of the shift register are information inputs of the device, the output of the shift register is connected to the first input of the first element And, the second input of which is connected to the output of the first trigger, the output of the first element And is connected to the first information input of the adder, the second, third, four the fourth and fifth information inputs of the first adder are connected to the outputs of the second, third, fourth and fifth triggers, the inputs of the first, second, third, fourth and fifth triggers are connected to the second, third, fourth, fifth and sixth outputs of the first decoder, the output of the first adder is connected to video input of a television indicator, the outputs of the second decoder are connected to the first inputs of elements AND groups, the second inputs of which are connected to the outputs of the third trigger, and the third inputs are with the output of the fifth trigger, the outputs of the elements And the groups are ₅₀ control outputs of the device, the output of the first pulse counter is connected to the first input of the second adder, the second input of which is connected to the output of the address register, the information input of which is the address input of the device, and the control one is the first control input of the device, the outputs of the second adder are address device outputs, characterized in that, in order to increase the speed of the device, it contains the first, second, third and fourth data registers, the first, second, third and fourth comparison blocks, sixth and seventh triggers, second pulse counter, second, third and fourth AND elements, outputs of the first, second, • third and fourth data registers are connected to the first inputs of the first, second, third and fourth comparison blocks, information inputs of data registers are the first, second, third and fourth control inputs of the device, the control inputs of the first and fourth data registers are the second and third control inputs of the device, the control inputs of the second and third registers data are the fourth control input of the device, the second input of the first comparison unit is connected to the output of the first pulse counter, the output of the first comparison unit is connected to the inputs Zeroing the first pulse counter and the sixth trigger and the first input of the second element And the second input of the second comparison unit is connected to the third output point counter and output 1399811 6 of the second comparison unit is connected to the input Setting the sixth trigger unit, the output of which is connected to the first input of the third AND element, the second input of the third comparison unit is connected to the second output of the line counter, and the output of the third comparison unit is connected to the input The setting of the seventh trigger unit, the second the input of the fourth comparison unit is connected to the output of the second pulse counter and to the third input of the second adder, the output of the fourth comparison unit is connected to the inputs Zeroing of the seventh trigger and the second counter pulses, the output of the seventh trigger of the third connected key element to the points _{e is} connected to the second input of the element And, the output of which is with the first input of the fourth And, the second input of which is POD-the fourth output of the counter, the output of the fourth element And is connected to the counting input of the first pulse counter, the output of the third element And connected to the fourth inputs of the elements And groups, the second input of the second element And is connected to the output of the seventh trigger, the output of the second element And is connected to the counting input of the second pulse counter. ₉ α L points L £ points Phage 2