SU1043732A1 - Device for displaying dynamic information on television receiver screen - Google Patents

Abstract

DEVICE FOR DISPLAYING DYNAMIC INFORMATION ON THE SCREEN OF A TELEVISION RECEIVER, containing a block. The memory, the video signal conditioner, the shift register and the counter on the Y coordinate, connected to the synchronizer, are different. so that, in order to simplify the device by reducing the volume of the memory block, it contains a record counter, a counter on the X coordinate, a first and second delay elements, a first and second AND elements, and an OR element, one of the outputs of which is connected to the inputs of setting zero counters ; the X and Y coordinates and the records are one of the control inputs of the device, the other; whose control input is the first input of the first element AND and one of the inputs of the second element AND, the other input of which is connected to the output of the overflow signal and the Y coordinate, the output of which is connected to one of the memory inputs of the memory block, the other address input of which is connected to the output of the counter on the X coordinate, and the output is connected to the input of the video signal conditioner, the output of which is the information output of the device, the input of which is the input of the shift register, the installation input of which is connected to the output of the element OR clocks, the input is connected to the output of the first delay element, and the output is connected to the input of the memory unit, the input (L о is connected to the input of the first delay element and the output of the first element I, the second input of which is connected to the output of the second delay element, the input of which is connected to the other output of the synchronizer, to the clock inputs of the counter along the X coordinate and the clock input of the counter whose output is the input of the first element AND, the other input of the element: o this OR is connected to the output of the second element AND and the tact (by indicating the input of the counter along the X coordinate. 9 ND

Description

The invention relates to computing technology and can be used in the construction of systems for displaying dynamic information on television indicators. A device is known for displaying dynamic information on a television indicator containing a group of storage elements, an addressing unit and an indicator l. The disadvantages of this device are the complexity of the organization of addressing and control and the large amount of memory required. The closest to the technical essence of the invention is a device for displaying dynamic information on the screen of a television receiver, containing two memory blocks, a switch, a video signal generator, a shift register, a counter along the Y coordinate, a synchronizer, control and interface units, a character generator, a converter and a color control unit 2. The disadvantages of the known device are its great complexity and the excessive volume of the memory block. The aim of the invention is to simplify the device for displaying dynamic information on the screen of a television receiver by reducing the size of the memory block. The goal is achieved by the fact that a device for displaying dynamic information on a television receiver's screen, containing a memory block, a video signal generator, a shift register and a counter along the Y coordinate, connected to the synchronizer 1, additionally contains a recording counter, a counter along the X coordinate, the first the second and second delay elements, the first and second elements AND, and the OR element, one of the inputs of which is connected to the inputs of setting zero counters in the X and Y coordinates and the record, is one of the control inputs of the device, We have a control input of which is the first input of the first element I and one of the inputs of the second element I, the other input of which is connected to the output of the counter overflow signal in the Y coordinate, the output of which is connected to one of the address inputs of the CGMI unit, the other address input of which is connected to the output of the counter by the coordinate X, and the output is connected to the input of the video signal former, the output of which is the information output of the device, the information input of which is the input of the shift register, the setup input connected to the output of the OR element, the clock input is connected to the output of the first delay element, and the output is connected to the input of the memory block whose recording enable input is connected to the input of the first delay element and the output of the first And element, the second input of which is connected to the output of the second delay element the input of which is connected to the other output of the synchronizer, with the clock input of the counter on the X coordinate and the clock input of the record counter, the output of which is connected to the third input of the first element And, another input of the IL element connected to the output of second AND input of the counter and a timing of the coordinate X. The figure is a functional diagram of the device. The device contains a synchronizer 1, a counter 2 on the X coordinate, a counter 3 entries, a counter 4 on the Y coordinate, a memory block 5, a delay element b, an AND 7 element, a delay element 8, a shift register 9, an AND 10 element, an OR 11 element, shaper 12 video. The device works as follows. In static display mode, the Shift signal is zero. On a short-term pulse signal Start, the circuit is prepared for operation. In this case, the signal is fed to the inputs of setting zero (f) of counter 2 along the X coordinate, counter 3 records and counter 4 along the Y coordinate, setting them to the zero state. Each dotted screen element corresponds to an addressed element of the 5th unit, the contents of counter 4 determine the number of the displayed line on the television screen, and the contents of counter 2 determine the number of the displayed element in the line. Thus, after the signal is sent, the Start from memory block 5 is selected at the specified address ... j, N pO ... 0, the contents of the first in order element in the first line, which goes to the driver 12 and then to the television receiver. The symbol N is the counter code 2, and the symbol M is the counter code 4. Synchronizer 1 generates a pulse (SI), which is fed to the counting input (C1) of counter 2. and increases its content by one digit. In this case, the second element of the first row is already read from memory block 5 at address A. J.OOO ... Q / 00 ... Qj With TJ Tl the next SI pulse arrives, the address of memory block 5 becomes And 0100 ... p, , 00 ... Oh,. Si And After the arrival of the next pulse, the SI code N increases and so on until it becomes equal to 11 ... 1. Since the counting coefficient of counter 2 is chosen equal to the number of elements in row (2), then after the arrival of the next SI pulse, the counter 2 is reset to its original zero state. Simultaneously with the last SI pulse, synchronizer 1 generates a row pulse (STI), which is fed to the counting input (C) of counter 4 and increases its contents by one. Thus, the address A 00 is set. .100 .... This means N M that from block 5 of memory is read, the second element of the second line. Next, the synchronizer generates a new series of SI pulses, and thus the second lines of the image are displayed. Simultaneously with the last impulse of the SI series, synchronizer 1 generates a line pulse, which sets a new address .00 0100 ... O ,. The operation of the N M device is repeated until the code M equals 11 ... 1. Since the counting factor of counter 4 is chosen equal to the number of lines of the screen (2), after the arrival of the next STI pulse, the counter 4 is set to the initial zero condition and the address A .00 ... 0. 0 is set at the input of memory block 5. 00 .. 0 .. After this, a new cycle of the device operation starts. In the dynamic display mode, the signal Shift Equal to Units. By the Start signal, the counter 2 is set, the counter 3 is recorded, the counter 4 is in the zero state and the column code of the image is written to the shift register 9. From memory block 5, it is selected to the address A .00 .. .0 ,, .00. . 0 contains N M of the first in order element in the first line, which enters the driver 12. Synchronizer 1 generates a series of pulses, which enters the counting input (C1) of the counter 2, its contents vary from 00 ... to 11 .. .1, and the counting input (C) of the 3-record counter, also its content is from 00 ... O to 11 ... 1. In the event that the contents of the 3-record counter become 11 ..., the AND 7 element opens and the pulse from the output of the delay element 6 passes the jHa input Record Resolution (MV) of the memory block 5. By this signal, the bit digit of the number stored in register 9 is recorded in memory block 5 at the specified address ii-LAi-L PO - 0 Pulse From the output of element 7, through element 8 of delay arrives at the shift input (C1) shift register 9 and shifts its contents by a bit. After the next SI pulse arrives, the counters 2 and 3 of the record are reset to the initial zero state. Simultaneously with the last SI pulse, the synchronization unit 1 generates a row pulse (STI), which is fed to the counting input (C) of the counter 4 and increases its contents by one. Thus, the address of the first element of the line is established. .- Synchronizer S and 1 generates a series of pulses, which is fed to the counting input (C) of counter 2, its contents vary from 0.0 ... O to 11 ... 1, and to the counting input (C) of counter 3 records, also change its contents are from 00 ... O to 11 ... 1. In this case, when the contents of the 3-record counter become 11 ... 1, element 7 opens and the pulse from the output of the delay element passes to the input Block Record Resolution 5 memories. By this signal, the second digit of the image code (the first digit of the number stored in the shift register) is recorded in the memory block 5 at the set address. D1 - Ij, 100 ... ABOUT,. A pulse from the output of the M yes element 7 And through the delay element 8 is fed to the shift input (C1) of the shift register 9 and shifts its contents by one bit. The device is working until the code M becomes equal to 11. 1. After the arrival of the next STI pulse, the counter 4 is set to the initial zero state and an overflow (P) of the output counter 4 appears in the pulse, which passes through the open element Ei to the subtractive input (C2) of the counter 3. The impulse from the output And 10 passes through the element OR 11 on the installation. new entry (C2) register 9 shift. This signal in the shift register 9 records the new code of the image column. Thus, to the new operation cycle of the device in the memory block 5, information on the addresses of all combinations of the value M is replaced; ... 1 (the last column of the image). It should be noted that by the beginning of the new cycle of operation of the device, a modification of the initial alignment of the row elements on the counter 2 was made. And the scan of the image (the contents of memory block 5) starts for all the lines from 1 to 1 K. 1 ,, M, where

M - a set of all combinations of the counter 4. In this work cycle, the recording of information from the shift register 9 will be carried out at the addresses

M. For the third cycle

A, 011.

N

the image scan starts for all lines from the address A p 11 ... 1 ,, M ,, and the recording is done

by addresses A

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By the CMM, by modifying the address of the memory block 5, the effect of moving the image appears on the screen

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Compared with the known device in the proposed device, the volume of the memory block is reduced. 2 times.

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Claims (1)

DEVICE FOR DISPLAYING DYNAMIC INFORMATION ON THE SCREEN OF A TV RECEIVER, containing a block, memory, a video signal conditioner, a shift register and a counter along the coordinate Y connected to a synchronizer, characterized in that, in order to simplify the device by reducing the size of the memory block, it contains a counter records, a counter along the X coordinate, the first and second delay elements, the first and second AND elements and an OR element, one of the outputs of which is connected to the inputs of setting the counters to zero at the X and Y coordinates and the recording is ne of the control device inputs the other control input of which is the first input element lane Vågå Ii odyn input of the second AND gate, the other input of which is connected to the output of the counter overflow signal to the coordinate Y, the output of which is connected to one of the address inputs of the memory block. another address input of which is connected to the output of the counter along the coordinate X, and the output is connected to the input of the video signal shaper, the output of which is the information output of the device, the information input of which is the input of the shift register, the installation input of which is connected to the output of the OR element, the clock input connected to the output of the first delay element, and the output is connected to the input of the memory unit, the recording permission input of which is connected to the input of the first delay element and the output of the first element And, the second input of which th connected to the output of the second delay element input koto-; It is connected to another synchronizer output, with a clock input of the counter along the X * coordinate and a clock input of the counter, the output of which is connected to the third input of the first AND element, the other input of the OR element is connected to the output of the second ”AND element and the clock input of the counter along the coordinate X. > I 104 3-742