SU1437908A1 - Device for output of graphic information - Google Patents

Abstract

The invention relates to automation and computer technology and can be used for implementing graphic information from a computer. The purpose of the invention is to expand the field of application of the device due to the possibility of viewing the image by the window of the screen vertically, which is achieved by the introduction of the element And 7, the counter 8, the adder 9, the register 10 and the corresponding functional connections. The device allows you to organize a quick review of the image by shifting it vertically up or down. 2 hp f-ly C 4 Il. with (L with:

Description

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The invention relates to automation and computer technology and is intended to output information from a computer.

The purpose of the invention is to expand the field of application of the device by allowing the image to be viewed vertically on the screen window.

FIG. 1 shows a block diagram of the device; Fig 2 - synchronization; in fig. 3 is a block diagram of a pulse distributor; on fcg 4 - change of addresses of reading information from the memory block when the image is shifted up or down.

The device contains a memory unit, a television indicator 2, a modulation unit 3, a distributor of 4 pulses, a synchronization unit 5, a KOMi-iyatator 6 of the address, an And 7 element, a counter 8, an adder 9, a register 10.

The synchronization block contains a generator P of pulses, a counter of 12 points, a counter of 3 lines, decoders 14, first trigger 15, second trigger 16, third trigger 17, fourth trigger 18, adder 19, one-shot 20.

The pulse distributor contains the shift register 21, the decoder 22, the third trigger 23, the fourth element And 24, the fifth element. And 25, the second group of elements And 26, the first group of elements And 27J the second trigger 28, the first 9th trigger 29, the first element And 30, the third element, And 31, the second element, And 32.

The device operates as follows.

The pulse generator 1 generates high frequency pulses corresponding to the required horizontal screen rasterization of the screen, which are fed to the counting input of a 12-point counter. The conversion factor of the counter 12 points corresponds to the TV standard for the duration of the line scan. The signal from the high-order output of the 12-point counter enters the counting input of a 13-row counter, which recalculates the image lines in a frame and has a conversion counter corresponding to the frame scan duration. The signals from the outputs of the counter 12 points and the counter 13 lines arrive at the information inputs of the decoder 14.

The decoder 14 generates control signals flip the first 1-5, second 16, third 17 and fourth

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five

0

five

0

five

0

five

0

five

18 triggers. The first trigger 15 generates signals of personnel protective bands; the second trigger 16 generates frame pulses; the third trigger 17 - signals lowercase protective stripes; the fourth trigger generates lowercase sync pulses. The components of the television sync mixture thus obtained are converted by the adder 19 into a standard sync signal, which is fed to the synchronous input of the television indicator 2,

Clock pulses from the generator output 11 pulses arrive at the clock input of the shift register 2b and the per-® input of the decoder 22. The low-order outputs of the counter 12 points go to the second input of the decoder 22 and the second, inputs of the first 27 and second 26 groups of elements AND..

Lower clock pulses from the output of the fourth trigger 18 are fed to the first input of the element 7, to the second input of which frame protection pulses are fed from the output of the first trigger 15. In addition, the frame protective pulses are fed to the control input of the address switch 6, to the second input the third element And 31 and to the input of the one-shot 20, which forms the impedance of the reset in O of the counter 8. The outputs of the higher bits of the counter 12 points are the fallen bits of the CJIOB read address from the memory 1 and recalculate the number of words Anchors in the image line.

In memory block 1, each bit of the screen corresponds to one bit, and the dotted display on the screen occurs when the unit is written to the corresponding bit of memory block 1. The latter is organized in the form of K-bits: words, and 2 words fit into one line of the image. Bcei o on the screen is placed M lines of the image. In memory block 1, information about the M-1 line of the image is stored, and your line is not displayed on the screen and is free. Counter 8 of image row addresses has a recalculation factor of M + 1 and is a binary counter.

Information is read from memory block 1 as follows.

From the computer in register 10 is entered the address of the Academy of Sciences of the initial line with

starts displaying information. The impulse of the end of the protective frame strip, coming from the synchronization unit 5, sets counter O to 8. At the same time, the signal of the protective protective band blocks the passage of the horizontal sync pulses from the synchronization unit 5 through the element 7 to the counting input of the counter 8. With the beginning of the visible frame stroke, the element 7 it is unlocked and the lower-case sync pulses begin to arrive at the counting input of counter 8. The output code of the counter 8, summed in the adder 9 with the initial address of the AI, recorded in register 0, is fed to the input of the higher bits of the address of the words in memory block 1 (the second address input),

The low-order bits of the addresses arrive at the first information input of the switch 6 of the address from the synchronization unit 5 and determine the recalculation of words in the string. Under the influence of pulses arriving from synchronization unit 5 to the distributor of 4 pulses, the latter produces a temporary readout diagram for memory unit 1, which ensures reading and transmission of information to modulation unit 3.

The distributor 4 pulses works as follows.

In the mode of reading information from memory block 1, it forms a timing diagram of a read cycle and controls the operation of modulation unit 3. The signals of the timing diagram of a read cycle are generated at the output of

Displays of the shift register 21, which, during the read cycle, pushes bit 1, and at the end of the cycle is reset to O by the signal from the output of the decoder 22. With the same cycle end signal, the third trigger 23, which tells tia which register and multiplexer is modulated, is thrown. unit 3 receives the recording signals from the outputs of the fourth 24 and fifth 25 And elements and the control signals of the multiplexers from the outputs of the first 27 and second 26 groups of elements I.

By signal The recording request to the control input of the device, the second trigger 28 is set to 1. From the beginning to the adroit protection band, the third element I 31 is allowed to pass the beginning of the pulses of the memory 1 block from the output of the decoder 22. The first

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the pulse of the beginning of the cycle sets to 1 the first trigger 29, which resets the second trigger to O. 28. The next pulse of the beginning of the cycle resets the first trigger 29 to O.

Thus, in the code of the first trigger 29, a pulse is formed equal in duration to one cycle of memory 1, which allows the recording strobe from the output of the shift register 21 to pass through the first element 30 to the recording input of memory 1, and this information. The signal of the end of the cycle from the output of the decoder 22, the passage through the second element And 32, serves as a signal to the end of the recording entering the computer. After that, the computer can set the next signal Record Requirement and begin to write the next word.

The last pass through the first element AND 7 on the visible frame stroke of the horizontal sync pulse sets the counter 8 to the state corresponding to the address of the free line so that the output of the adder 9 is set to ad20

25

res a se And c + M + 1, and the adder has log-1 (M + 1) aezrs, the transfer signal from the higher bit does not increase.

The signal of the personnel protective band entering the distributor of 4 pulses permits the transition to the recording mode in memory block 1. Information is recorded in memory block 1 only in the free line during the frame protection band. For this, information corresponding to the recorded word is supplied to the information inputs of the memory unit 1, and the address of the word AX in the line is set to the second input of the address switch 6. When a pulse is applied, the requirement of recording from a computer to the distributor of 4 pulses, the latter generates a recording signal, so that information is recorded in the corresponding cell. After that, a free line is written to the next cells in the same way.

To shift the image, it is now sufficient to change address A by one (in register 10, with A f + 1 corresponding to the image shift upwards.

a a

corresponds to the offset down

(Fig. 4).

Thus, it has only one free non-displayable frame.

line, organizing in it the appropriate modification of the information and setting the necessary a, Cres Ats, you can organize a quick viewing of the image by shifting it vertically up or down.

Claims (3)

1. A device for outputting graphical information comprising a memory unit, a modulation unit, a television indicator, a pulse distributor, a synchronization unit, an address switch, the outputs of the memory unit are connected to the information inputs of the modulation unit whose output is connected to the video input of the television indicator The first and second outputs of the pulse distributor are connected to the first and second control inputs of the memory unit, the control input of the distributor, pulses. is the recording control input of the device, the first and second synchronous inputs of the pulse distributor are connected to the first and second outputs of the synchronization unit, the third output of which is connected to the synchronous television indicator, the fourth output of the synchronization unit is connected to the first information input of the address switch, whose code is connected with the first address input of the memory unit, the third output of the pulse distributor is the output of the device recording windows 1, the outputs of the pulse distributor group are connected to the control inputs of the modulation unit, the second information input of the address switch is the first address input of the device, the five synchronization block is connected to the control input of the address switch and the clock input of the pulse distributor, the information input of the memory block is the information input of the device, different that, in order to expand the scope of application by providing the possibility of viewing the image by the window of the screen vertically, the element I, the counter, the adder and the register, the information The input of which is the second address input of the device, and the output is connected to the first information input of the adder, the output of which is connected to the second address input of the memory unit, and the second information input of the adder is connected to the output of the counter with the sixth output of the synchronization unit, the seventh output of which is connected to the first input of the element I, the output of which is connected to the counting input of the counter a, and the second input of the element I connected to the fifth output of the synchronization unit, the control input register and it is a second control input of the device. 2, The device according to p. one characterized in that the synchronization unit comprises a pulse generator, a point counter, a row counter, a decoder, first, second, third and fourth triggers, a one-shot and an adder, the first, second, third and fourth information inputs of which are connected to the outputs of the first, second, third and fourth triggers, the inputs of the Installation in 1 of which are connected to the first, second, third and fourth outputs of the decoder, respectively, the first and second information inputs of which are connected respectively to the first output of the point counter and the output of the row counter, the counting input of which is connected to the second output of the point counter, the counting input of which is connected to the output of the pulse generator, the one-vibrator input is connected to the output of the first trigger, the output of the pulse generator is the first output of the block, the third output of the point counter is the second output The block output of the adder is the third output of the block, the fourth output of the point counter is a quarter of the output of the block, the output of the first flip-flop is the fifth output of the block, the output of the one-shot is the sixth output of the block The fourth trigger output is the seventh block output. 3. The device according to claim 1, characterized in that the pulse distributor comprises a shift register, a decoder, the first, second and third triggers, the first, second, third, quarter and five And elements, the first and second groups of And elements, the first output of the shear the register is connected to the first input of the first element I, the second input of which and the first input of the second element I are connected to the first output of the first trigger, the second output of which is connected to the input Set to O of the second trigger, the output of which is connected to the input Set to About the first trigger a, input. The installation in 1 of which is connected to the output of the third element And, the first, input of the third element And connected to the first output of the decoder, the second output of which is connected to the input Set to 1 of the third trigger, the second input of the second element And the input of the distributor , the second input is the third1 about Setting in About the shift register, the third output of the decoder is connected to the first inputs of the fourth and fifth elements And, the first output of the third. the distributor, the output of the first element of the trigger is connected to the second input 15 and AND is the second output of the AND distribution element and the first inputs of the second, the output of the second I element is the AND elements of the first group, the second is the third output of the distributor, the third the trigger is connected to the second outputs of the fourth, fifth And elements, the eye with the input of the fourth element And and the elements of the first and second groups in- with the first inputs of the elements And the second 20 are output from the distribution of the group, the input is set to 1 of the second. tel. the trigger is the control input of the distributor, the clock input of the shift register is connected to the first input of the decoder and is the first synchronous input of the distributor, the second input of the decoder is connected to the second inputs of the elements of the first and second groups and is the second synchronous input. And is the clock input of the allocator, the second output of the shift register is the first output and 12 Qbl.21,22 : Shishshshsh Kfffl 22.2ff, 27 Have /{ff.S Fi.2 distributor, the second input is the third about the trigger is the control input of the distributor, the clock input of the shift register is connected to the first input of the decoder and is the first synchronous input of the distributor, the second input of the decoder is connected to the second inputs of the elements of the first and second groups and is the second synchronous input distributor, the second input is the third about the distributor, the output of the first element And is the second output of the distributor, the output of the second element And is the third output of the distributor, the outputs of the fourth, fifth elements And elements of the And the first and second groups are the outputs of the distributor. And is the clock input of the allocator, the second output of the shift register is the first output 13 P. f 15 G6 / 7 78 ecu KVl.7  К5л..6.7 f f f f 20 13 V .2 B “B one §§ iC I I Se and sh : n t  i ll SI II h five: It h: